Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[eek2121]

The difference between the spec testing vs the CB testing is way higher than one would expect, even if Zen 4 is more efficient in INT workloads.

You would want to compare 8+16 with a 12 core AMD processor, not a 16 core one, if you want to try to equalize "core counts"
But honestly, we don't even have to do that. Why bother with the little cores ruining GLC vs Zen 3/Zen 4 perf/watt testing? Just compare a 12400 vs 7600x. Or RPL with e-cores disabled vs a 7600x. Though that perf data is hard to come by from what I've seen.

AMD bins differently from Intel, so the *50 chips always have the fastest cores, and no, you absolutely should not be disabling e-cores on an Intel chip unless you are measuring P-core performance.

Since 2 e cores are supposed to have as much throughput than 1 P core using SMT it s straightforward that 16 e cores are the equivalent of 8 P cores, so 13900K vs 7950X is the adequate comparison.

Incorrect. 4 E-cores = 1 P-core. Each cluster of 4 E-cores shares 1 ring stop along with a variety of other resources. Please stop spreading misinformation.

 

[TESKATLIPOKA]

Incorrect. 4 E-cores = 1 P-core. Each cluster of 4 E-cores shares 1 ring stop along with a variety of other resources. Please stop spreading misinformation.

There is no such thing as 4 E-cores = 1 P-core when we compare performance.

Comparing 13900K(8P+16E) to 7950X is fair comparison.

edit:
8 P-cores + HT at 5.2GHz are comparable to 16 E-cores at 4.5GHz when It comes to MT performance.
If we were talking about power consumption or die size, then 16 E-cores would be much better than 8 P-cores.

 

[eek2121]

There is no such thing as 4 E-cores = 1 P-core when we compare performance.
View attachment 86417View attachment 86419
Comparing 13900K(8P+16E) to 7950X is fair comparison.

(Absolute) Performance has nothing to do with it! Execution resources are shared between each 4-core cluster. Intel is only changing this in an upcoming Xeon release.

All current designs are 4E = 1P. Intel has officially stated this!

One of the reasons Intel went with their hybrid design was that each big core required a single ring stop. Intel couldn’t easily release a 12-16 core chip because it would add too many stops to the ring. So what did they do? they made each quad core cluster share a ring stop, which allowed them to add more cores. And it worked.

That is one of the big reasons why there was a regression from 10 -> 8 cores for Alder Lake. It was to make room for the “e” cores. Intel could’ve released a 10 core part, but found that despite the cores sharing a ring stop (among other things) they could still perform sufficiently for client workloads.

4 “e” cores are “about” the size of a “P” core.

4 “e” cores will perform well in multicore workloads, but may struggle with some throughput stressing workloads due to limited caches and shared ring stops. If I ever get my hands on a 14900k I will write a benchmark to illustrate the strengths/weaknesses of Intel’s approach.

Intel Xeons use a higher latency meshed-based design btw, so they aren’t subject to limits.

AMD has not disclosed their design, but AnandTech has speculated on it. I won’t.

That is why the 8P+32E rumors aren’t very credible. Unless Intel has improved their design, Those extra 16 cores are adding several more ring stops, which will raise latency between cores and limit overall throughput (tl;dr diminishing returns based on number of cores added)

They could move everything to a mesh, but they would be at a competitive disadvantage. I suspect they will eventually get there, but not without other innovations.

The x86-64 architecture as a whole is on the edge of an evolution as well, and both Intel and AMD have their own visions of what that looks like.

 

[coercitiv]

There is no such thing as 4 E-cores = 1 P-core when we compare performance.

Use 1P=2E when you calculate absolute performance, use 1P=4E when you allocate cores for a fixed die area.

Comparisons need an ISO criteria: it can be die area, power, price. Depending on this criteria the core equivalence changes. This shouldn't even be a point of contention.

 

[TESKATLIPOKA]

(Absolute) Performance has nothing to do with it! Execution resources are shared between each 4-core cluster. Intel is only changing this in an upcoming Xeon release.

All current designs are 4E = 1P. Intel has officially stated this!

One of the reasons Intel went with their hybrid design was that each big core required a single ring stop. Intel couldn’t easily release a 12-16 core chip because it would add too many stops to the ring. So what did they do? they made each quad core cluster share a ring stop, which allowed them to add more cores. And it worked.

That is one of the big reasons why there was a regression from 10 -> 8 cores for Alder Lake. It was to make room for the “e” cores. Intel could’ve released a 10 core part, but found that despite the cores sharing a ring stop (among other things) they could still perform sufficiently for client workloads.

4 “e” cores are “about” the size of a “P” core.

4 “e” cores will perform well in multicore workloads, but may struggle with some throughput stressing workloads due to limited caches and shared ring stops. If I ever get my hands on a 14900k I will write a benchmark to illustrate the strengths/weaknesses of Intel’s approach.

Intel Xeons use a higher latency meshed-based design btw, so they aren’t subject to limits.

AMD has not disclosed their design, but AnandTech has speculated on it. I won’t.

That is why the 8P+32E rumors aren’t very credible. Unless Intel has improved their design, Those extra 16 cores are adding several more ring stops, which will raise latency between cores and limit overall throughput (tl;dr diminishing returns based on number of cores added)

They could move everything to a mesh, but they would be at a competitive disadvantage. I suspect they will eventually get there, but not without other innovations.

The x86-64 architecture as a whole is on the edge of an evolution as well, and both Intel and AMD have their own visions of what that looks like.

@Abwx was clearly talking about performance, even @Geddagod who he quoted talked about performance at the end of his post.
Yet you called him out to stop the misinformation? There was no misinformation, you just changed the criteria.

From when ring stop or shared L2 cache is an execution resource?

Current designs(Alder, Raptor) are physically: 2P+8E, 6P+8E, 8P+8E, 8P+16E
Meteor Lake will be 2P+8E and 6P+8E as far as I know.

Top Raptor Lake also has 12 ring stops(8P+16E), so this doesn't look as such a big issue.
The main issue is that P-core is big and very power hungry. Using E-cores saved both die space and power budget.

 

[Abwx]

Incorrect. 4 E-cores = 1 P-core. Each cluster of 4 E-cores shares 1 ring stop along with a variety of other resources. Please stop spreading misinformation.

All numbers point to the fact that you are misinformed on this issue, if 4 e = 1P then the 13900K would need 32 e cores to match the 7950X, or have a P core 2 x more powerfull than a Zen 4 core...

At 88 watts, the 7700x has ~35% more perf/watt than a 12900k with only 8 P-cores.
This isn't really ideal, considering I doubt RWC brings more than a 20% increase in perf/watt, meaning Intel would be behind (big core vs big core) by ~10% in perf/watt, but whatever.

Relevant comparison of 8C vs 8C is at equal throughput, why should a CPU be asked to have 35% more work done for a perf/watt comparison knowing that the higher the perf the lower the perf/watt..?..

Then why not compare the efficency at 65W for the 7700X and 125W for the e core less 12900K..?..

Because it would handicap the 12900K P cores..?..

How surprising...


Beside i m talking of handbrake because some pointed that perf/watt difference is bigger in SPECint than in CB, so with Handbrake we have a INT code test that can be used as comparison with Cinebench wich is FP, and the difference effectively apply, wich validate SPECint numbers.

 

[Geddagod]

AMD bins differently from Intel, so the *50 chips always have the fastest cores, and no, you absolutely should not be disabling e-cores on an Intel chip unless you are measuring P-core performance

Considering we were comparing GLC vs Zen 4, disabling E-cores is what we should have done. Which is why I was just so baffled @Abwx was comparing a 13900k to a 7950x.

@Abwx was clearly talking about performance, even @Geddagod who he quoted talked about performance at the end of his post.
Yet you called him out to stop the misinformation? There was no misinformation, you just changed the criteria.

Idk why you feel the need to white knight him so bad lol, but we were talking about perf/watt, not just outright perf. Obviously using 4-ecores (which is the reality of the situation) would increase perf/watt compared to comparing Intel and AMD skus where 2 e-cores = 1p core.
Also, counting 4-ecores as 1 P-core isn't "equalizing for performance" it's literally "equalizing for if Intel never made E-cores" in the first place.
But perhaps the dumbest part of the entire arguement was that the point of the claim was to try comparing GLC vs Zen 4 perf/watt, so using a product with e-cores in it is just hilariously stupid.

All numbers point to the fact that you are misinformed on this issue, if 4 e = 1P then the 13900K would need 32 e cores to match the 7950X, or have a P core 2 x more powerfull than a Zen 4 core...

You don't equalize it that way because that's not what an Intel that never developed E-cores would look like. It's really quite simple. The reason Intel doesn't need 32 e-cores to match the 7950x is 2 fold a)they clock all the cores sky high to match the 7950x (relative to their ideal clocks) b) e-cores simply are better for perf/area than P-cores. That's the entire point of the E-cores.

Relevant comparison of 8C vs 8C is at equal throughput, why should a CPU be asked to have 35% more work done for a perf/watt comparison knowing that the higher the perf the lower the perf/watt..?..

This makes 0 sense lol, and you have no idea what perf/watt is. Please stop confusing perf/watt with watts/perf. Because they give very different numbers.

Then why not compare the efficency at 65W for the 7700X and 125W for the e core less 12900K..?..

Because it would handicap the 12900K P cores..?..

How surprising...

You can if you would want too. It's just wrong to call it perf/watt, because that's not what it is lmao. You have 0 understanding of the term.
Also you do realize comparing perf/watt vs watt/perf isn't "handicapping" anything, right? That's not how it works....

Beside i m talking of handbrake because some pointed that perf/watt difference is bigger in SPECint than in CB, so with Handbrake we have a INT code test that can be used as comparison with Cinebench wich is FP, and the difference effectively apply, wich validate SPECint numbers.

In handbrake, 8x Zen 4 cores use >50% the power to match 8x GLC cores. In Specint, it's like 30-40%. It doesn't validate any numbers.

 

[Geddagod]

There was no misinformation, you just changed the criteria.

There was no overlying criteria in the first place other than what the "competition" would be. For example, this entire debate started when he said that MTL 6+8's competitor would be a hypothetical 10 core Zen 4 mobile cpu, not a 8 core one, for perf/watt comparisons. Which is just dumb. If Intel didn't develop e-cores, it would have had 8 P-cores.

 

[Geddagod]

I'm just going to end our conversation about this topic with @Abwx, by saying this:
You have no clue what perf/watt is, you don't even double check your math, and finally by pretending that product comparisons between e-cores and p-cores is in a 2:1 ratio just makes a mockery of idk, common sense, since if Intel didn't use e-cores at all, they would replace each 4-ecore cluster with a P-core. The only reason you want to compare perf/watt with using 2 e cores = 1 p core is so that Intel looks worse than it really is, just like when you want to use power iso perf so badly vs the much less "surprising" data of perf/watt, despite perf/watt being the more common industry standard measurement. Which, honestly, I wouldn't even mind that much lol, if you actually call it for what it is rather than incorrectly calling perf/watt.

 

[Abwx]

I'm just going to end our conversation about this topic with @Abwx, by saying this:
You have no clue what perf/watt is, you don't even double check your math, and finally by pretending that product comparisons between e-cores and p-cores is in a 2:1 ratio just makes a mockery of idk, common sense, since if Intel didn't use e-cores at all, they would replace each 4-ecore cluster with a P-core. The only reason you want to compare perf/watt with using 2 e cores = 1 p core is so that Intel looks worse than it really is, just like when you want to use power iso perf so badly vs the much less "surprising" data of perf/watt, despite perf/watt being the more common industry standard measurement. Which, honestly, I wouldn't even mind that much lol, if you actually call it for what it is rather than incorrectly calling perf/watt.

I made comparisons with e cores disabled, and since previously you said that it wasnt that relevant i pointed tests done a 12900K with e cores disabled so we can compare to a 7700X, seems that it s not relevant as well according to your post, so nothing is relevant as long as it doesnt support your flawed naratives...

As for perf/watt it s you who dont know what you are talking about since you re comparing CPUs at different throughput, wich is a flaw.

To give an exemple let s use the retarded car comparison.

Say a car that consume 10l/100km and the other 5l/100km.

If you travel 100km at 100km/h the second car will use 5l.

Your methodology is to make the fist car travel at 75km/h over a 75km distance, so its 10l/100km efficency become something like 7l/100kmh while shortening the distance to 75km.

That s your perception of perf/watt, to test at different performance levels, wich in the case of CPU is to make a CPU accomplish less work over a given time and then state that when it does less work per second it has not that much inefficency.

Comparatively to a car you are mesuring the less efficent one comsumption for a 75km travel at lower speed while the most efficient has its comsumption measured for a 100km travel at higher speed and then state that they consume equivalent amount of gas...

 

[Geddagod]

Intel4/RWC needs magic to do so.

As someone tested, at 5.2Ghz 1T Zen4 use only 30% of power of a GLC(or RaptorCove) and 2T <50% of power.

Nobody could tell if GLC is bugged or not. If yes RWC has a chance to get fix.

https://twitter.com/i/web/status/1702629569834938549

View attachment 86389


View attachment 86390

Oh and I forgot to respond to this. See, this is exactly why using the "perf/watt" and "watts/perf" interchangeably as if they were the same thing is so confusing. RWC doesn't need "magic" to fix this. The reason this looks so much worse than it really is, is bcuz people are looking at "20% better perf/watt" and going, that can't fix a core when it's competitor is using 40% the power iso perf, right?

Using the 40% figure at the lowest end of the graph, RWC would end up using 15 watts, or around 35% more energy iso perf. A far cry from the >2x figure of GLC vs Zen 4. However, that's also at the lowest end of the frequency curve. Look at the difference when both cores are pushed to the max at very high power consumption (such as what's happening in this specint test, when both cores are hitting 5.3 GHz) - Intel 4 here sees a 60% reduction in power. Apply this figure to GLC- you see it drawing 10 watts, meaning Zen 4 here actually has to consume 10% more energy iso perf with RWC.

Perf/watt means perf iso watts. The denominator is equalized, not the numerator. That's how everyone uses the term, pretending otherwise makes everything more confusing.

 

[Abwx]

Perf/watt means perf iso watts. The denominator is equalized, not the numerator. That's how everyone uses the term, pretending otherwise makes everything more confusing.

Perf/watt improvement is something else, take a given CPU that work at say 3GHz, keep the same CPU and shrink the process, and then measure power at the same frequency and hence throughput and you ll get the perf/Watt improvement of the process.

Beside you re making a big mistake because you dont pay attention to the numbers, if we are to follow the Intel 7 curve then GLC power double from 3.1 to 3.3Ghs, wich is abolutely non sense, so it s obvious that something is wrong in this curve...

 

[TESKATLIPOKA]

Idk why you feel the need to white knight him so bad lol, but we were talking about perf/watt, not just outright perf. Obviously using 4-ecores (which is the reality of the situation) would increase perf/watt compared to comparing Intel and AMD skus where 2 e-cores = 1p core.
Also, counting 4-ecores as 1 P-core isn't "equalizing for performance" it's literally "equalizing for if Intel never made E-cores" in the first place.
But perhaps the dumbest part of the entire arguement was that the point of the claim was to try comparing GLC vs Zen 4 perf/watt, so using a product with e-cores in it is just hilariously stupid.

What white knighting him so bad?
Just because I said he was talking about performance?

@eek2121 quoted a part where @Abwx talked about performance.
In that case, It's 2 E ~= 1 P

If you or eek2121 want to compare other criteria like die size or power consumption, then yes, It would(could) be 4 E ~= 1 P.

I can agree, that for comparing GLC to Zen4, enabling E-cores is wrong.

There was no overlying criteria in the first place other than what the "competition" would be. For example, this entire debate started when he said that MTL 6+8's competitor would be a hypothetical 10 core Zen 4 mobile cpu, not a 8 core one, for perf/watt comparisons. Which is just dumb. If Intel didn't develop e-cores, it would have had 8 P-cores.

If I compared only performance, then I would say MTL 6+8 is comparable to a hypothetical 10C Zen4. But It doesn't exist, so It leaves me with 8C16T Phoenix only.
As for perf/W I am not sure what to compare It with.

At least when both MTL and Strix are out, we can compare
4(6)P+8E MTL to 4+8 Strix to see perf, perf/W, die size etc.

 

[Mopetar]

Beside you re making a big mistake because you dont pay attention to the numbers, if we are to follow the Intel 7 curve then GLC power double from 3.1 to 3.3Ghs, wich is abolutely non sense, so it s obvious that something is wrong in this curve...

It's not that far off from what would be expected mathematically. Going from .85 V to 1.1 V would increase the power draw by 66%. The frequency bump takes it to a little under 80% increase in power. Treat it more like an increase from 3 GHz to 3.4 GHz and it's a 90% power increase.

 

[Abwx]

It's not that far off from what would be expected mathematically. Going from .85 V to 1.1 V would increase the power draw by 66%. The frequency bump takes it to a little under 80% increase in power. Treat it more like an increase from 3 GHz to 3.4 GHz and it's a 90% power increase.

I noticed the thing, but something that work at 0.85V@3GHz doesnt need that much voltage uplift to reach 3.4GHz.

Considering Intel 7 typical frequency/voltage curves 5.6% higher voltage is enough, that s 0.898V at most, so at 1.1V they are overestimating the necessary voltage by 22.55% and the resulting power by 50%, wich has the "virtue" of displaying Intel 4 much better than it really is.

 

[Geddagod]

I noticed the thing, but something that work at 0.85V@3GHz doesnt need that much voltage uplift to reach 3.4GHz.

That's not true if the architecture Fmax is only like 3.4Ghz.

Considering Intel 7 typical frequency/voltage curves 5.6% higher voltage is enough, that s 0.898V at most, so at 1.1V they are overestimating the necessary voltage by 22.55% and the resulting power by 50%, wich has the "virtue" of displaying Intel 4 much better than it really is.

What?
Intel 7 and GLC exhibits a very similar power scaling when they hit close to their Fmax. 8xGLC cores at 5.2GHz consume 75% more energy than 8xGLC cores at 4.7GHz. So a 75% increase in energy for 10% better perf.
The Intel 4 graph has Intel 7 present very similar characteristics at the frequency of 3.2GHz, vs 2.9Ghz you are getting ~10% better perf, but consuming ~63% more energy.
The closer you get to the Fmax of any architecture, the more power you have to consume to increase performance by the same % vs previous frequencies.

Beside you re making a big mistake because you dont pay attention to the numbers, if we are to follow the Intel 7 curve then GLC power double from 3.1 to 3.3Ghs, wich is abolutely non sense, so it s obvious that something is wrong in this curve...

These cores aren't GLC vs RWC, it's a random arm core. There's nothing wrong with the curve.
Intel didn't change the graph or anything, this was presented at an academic conference not just your generic unlabeled marketing graph for the public. The worst Intel could have done is purposefully handicap the DTCO design process with Intel 7 vs Intel 4 on the core.
Though I will say, I think Intel standardizing perf/power results based on actual designs is a good thing. Gate measurements don't translate perfectly into actual products, so I think Intel showing "we can get these results in actual cores" is a good thing. Plus, I'm pretty sure that's how the rest of the industry (TSMC and Samsung) do it as well.

 

[Abwx]

That's not true if the architecture Fmax is only like 3.4Ghz.

What?
Intel 7 and GLC exhibits a very similar power scaling when they hit close to their Fmax. 8xGLC cores at 5.2GHz consume 75% more energy than 8xGLC cores at 4.7GHz. So a 75% increase in energy for 10% better perf.
The Intel 4 graph has Intel 7 present very similar characteristics at the frequency of 3.2GHz, vs 2.9Ghz you are getting ~10% better perf, but consuming ~63% more energy.

Nowhere i see 4 or 5GHz on the curve below, so there s no conclusions that can be made about Intel 4 actual perfs at those frequencies.

These cores aren't GLC vs RWC, it's a random arm core. There's nothing wrong with the curve.

So they display a curve that is irrelevant for the product we re talking about, set apart for low clocked SKUs and with the bias i pointed.

Even with an ARM core the curve does not make sense, a transistors is a transistor, it will scale the same way in whatever uarch within such low frequencies, we re talking of 3GHz here, and i never saw a process and CPU that would require that huge of a voltage uplift to gain that small increasement in frequency.

 

[H433x0n]

So they display a curve that is irrelevant for the product we re talking about, set apart for low clocked SKUs and with the bias i pointed.

It’s very relevant for displaying data on the process tech and to provide a proper basis to compare previous nodes. There is no bias in this chart, it’s a technical document. It’s industry standard practice.

Even with an ARM core the curve does not make sense, a transistors is a transistor, it will scale the same way in whatever uarch within such low frequencies, we re talking of 3GHz here, and i never saw a process and CPU that would require that huge of a voltage uplift to gain that small increasement in frequency.

Feel free to compare it to similar data released from TSMC & Samsung.

 

[Geddagod]

Feel free to compare it to similar data released from TSMC & Samsung.

Yup, like right here:


I genuinely don't think @Abwx has a clue about what he's talking about at this point. Should have taken your suggestion of just not responding too him with him not responding in good faith.
It's actually sad that we have to discuss the validity of a presentation at IEEE VLSI symposium.
Just gonna stop responding to him smh.

 

[coercitiv]

I genuinely don't think @Abwx has a clue about what he's talking about at this point.

Abwx is competent and smart, but stubborn as a mule and convinced that most other people are less than well prepared (to use an euphemism). Add a language barrier and the fact that most of the time we work with indirect data sources and napkin math, and we have a recipe for disaster in communication. Most of the time it ends up with people talking at each other with different premises and reasoning in mind. One such example is him expecting to derive GLC data from that Intel 7/Intel 4 v/f graph while you were just trying to discuss node properties. The resulting exchange is pointless, like most of the discussion on power efficiency in the other thread (or in this one, I can't tell anymore).

Moving away from this debate, one thing that stuck in my head after seeing that graph again last night, is the frequcny scaling for Intel 4. It's interesing that in the sub-4Ghz range the new node performs better than Intel 7 (as one would expect), and yet we know MTL is subject to lower fmax in the 5Ghz range than RPL. The two facts are not necessarily ot odds with eachother, but it makes me curious to see whether this ends up being the result of the new P core design (kinda unlikely), node frequency scaling in the higher region, or maybe even a deliberate choice by Intel to opt for density optimisation in their mobile lineup.

 

[Geddagod]

Abwx is competent and smart, but stubborn as a mule and convinced that most other people are less than well prepared (to use an euphemism). Add a language barrier and the fact that most of the time we work with indirect data sources and napkin math, and we have a recipe for disaster in communication. Most of the time it ends up with people talking at each other with different premises and reasoning in mind. One such example is him expecting to derive GLC data from that Intel 7/Intel 4 v/f graph while you were just trying to discuss node properties. The resulting exchange is pointless, like most of the discussion on power efficiency in the other thread (or in this one, I can't tell anymore).

Moving away from this debate, one thing that stuck in my head after seeing that graph again last night, is the frequcny scaling for Intel 4. It's interesing that in the sub-4Ghz range the new node performs better than Intel 7 (as one would expect), and yet we know MTL is subject to lower fmax in the 5Ghz range than RPL. The two facts are not necessarily ot odds with eachother, but it makes me curious to see whether this ends up being the result of the new P core design (kinda unlikely), node frequency scaling in the higher region, or maybe even a deliberate choice by Intel to opt for density optimisation in their mobile lineup.

Lower Fmax vs RPL could be attributed to a combination of these factors:
lower fin counts (using HP instead of UHP)
Low volume so binning has to be more flexible
pretty likely DTCO improvements from RPC>GLC didn't track into RWC (considering MTL and RPL had pretty close to parallel development timelines)
Slight architecture changes (L1D edit: L1I mb in particular could make clocking high harder)
RPL uses Intel 7+ rather than Intel 7 (as shown in the graph)

In comparison to ADL in mobile, MTL actually has a 200MHz Fmax advantage.
A pretty common problem, IMO, for Intel, is that since they have been delaying their nodes for so long, the node behind it gets extremely mature, the architecture behind it gets insanely optimized, and the binning for it becomes extremely well tuned. Kinda handicaps how high they can say their "next gen" product improves upon the previous one in some aspects.

 

[DrMrLordX]

Moving away from this debate, one thing that stuck in my head after seeing that graph again last night, is the frequcny scaling for Intel 4. It's interesing that in the sub-4Ghz range the new node performs better than Intel 7 (as one would expect), and yet we know MTL is subject to lower fmax in the 5Ghz range than RPL. The two facts are not necessarily ot odds with eachother, but it makes me curious to see whether this ends up being the result of the new P core design (kinda unlikely), node frequency scaling in the higher region, or maybe even a deliberate choice by Intel to opt for density optimisation in their mobile lineup.

Sadly we'll probably never see compute tiles on Intel 4 in another product, so there won't be any way to run comparisons and learn more.

 

[eek2121]

Lower Fmax vs RPL could be attributed to a combination of these factors:
lower fin counts (using HP instead of UHP)
Low volume so binning has to be more flexible
pretty likely DTCO improvements from RPC>GLC didn't track into RWC (considering MTL and RPL had pretty close to parallel development timelines)
Slight architecture changes (L1D edit: L1I mb in particular could make clocking high harder)
RPL uses Intel 7+ rather than Intel 7 (as shown in the graph)

In comparison to ADL in mobile, MTL actually has a 200MHz Fmax advantage.
A pretty common problem, IMO, for Intel, is that since they have been delaying their nodes for so long, the node behind it gets extremely mature, the architecture behind it gets insanely optimized, and the binning for it becomes extremely well tuned. Kinda handicaps how high they can say their "next gen" product improves upon the previous one in some aspects.

Yes, on (and before) 14nm Intel power limits really began creeping up because they fell behind on process, so they hyper optimized everything and raised power targets to the moon so they could eke out every single MHz. Only, the next process doesn’t scale so well with power limits without changes to the cores or the process itself (in the case of Intel 7), so they end up releasing junk like ice lake core i3s in order to get things running while they do it all over again.

Hitting 6ghz on Intel 20a/18a is several orders of magnitude harder than it is on Intel 7+, but if they regress clocks, they need a large IPC increase to compensate for a clock regression. Even a drop to 5ghz requires > 20% IPC increase. The new product also needs to be faster than the old one, so really you are looking at a 25-35% increase, which is very difficult to pull off, so what is Intel going to do? I don’t know, but if Meteor Lake is representative of things moving forward, it looks like minor IPC gains for the next few generations while they either get chips on the new process to hit higher clocks or increase IPC enough over time to make up for it.

I will be absolutely floored if Intel manages to get Arrow Lake to 5.8-6ghz on a “2nm” class process. If they do, at least it will be more power efficient.

Honestly, if I were Intel I would have avoided the Raptor Lake Refresh frequency jump. Don’t even release a 14900k. Increase the core counts of lower tier parts, sure. That should keep OEMs happy.

Now they have a 6ghz (4.4ghz on the e-cores) 8+16 part coming out that is going to consume 350+ watts peak and their next chip is going to have to beat it in terms of absolute performance since perf/watt is not marketable outside of mobile. Heh, good luck, Intel.

 

[inf64]

Yes, on (and before) 14nm Intel power limits really began creeping up because they fell behind on process, so they hyper optimized everything and raised power targets to the moon so they could eke out every single MHz. Only, the next process doesn’t scale so well with power limits without changes to the cores or the process itself (in the case of Intel 7), so they end up releasing junk like ice lake core i3s in order to get things running while they do it all over again.

Hitting 6ghz on Intel 20a/18a is several orders of magnitude harder than it is on Intel 7+, but if they regress clocks, they need a large IPC increase to compensate for a clock regression. Even a drop to 5ghz requires > 20% IPC increase. The new product also needs to be faster than the old one, so really you are looking at a 25-35% increase, which is very difficult to pull off, so what is Intel going to do? I don’t know, but if Meteor Lake is representative of things moving forward, it looks like minor IPC gains for the next few generations while they either get chips on the new process to hit higher clocks or increase IPC enough over time to make up for it.

I will be absolutely floored if Intel manages to get Arrow Lake to 5.8-6ghz on a “2nm” class process. If they do, at least it will be more power efficient.

Honestly, if I were Intel I would have avoided the Raptor Lake Refresh frequency jump. Don’t even release a 14900k. Increase the core counts of lower tier parts, sure. That should keep OEMs happy.

Now they have a 6ghz (4.4ghz on the e-cores) 8+16 part coming out that is going to consume 350+ watts peak and their next chip is going to have to beat it in terms of absolute performance since perf/watt is not marketable outside of mobile. Heh, good luck, Intel.

Pretty much this, I think you nailed it. Intel will now have a higher IPC core that will clock significantly lower. Let's see what the reviewers and end users will say about that.

 

[Abwx]

Yup, like right here:
View attachment 86458

I genuinely don't think @Abwx has a clue about what he's talking about at this point. Should have taken your suggestion of just not responding too him with him not responding in good faith.
It's actually sad that we have to discuss the validity of a presentation at IEEE VLSI symposium.
Just gonna stop responding to him smh.

To understand things one should be capable of understanding the numbers and the subjacent maths, wich is not your case, prove is that you dont even notice the difference between what TSMC provided and what Intel displayed...

In this TSMC pic we can see that from 1.4 to 3.6GHz voltage increase from 0.6V to 1.1V, that s 1.83x more voltage for 2.57x higher frequency, and that s a typical voltage frequency curve wich is realistic.

Now compare with what Intel provided, where voltage of Intel 7 is increased by 1.29x for a meager frequency uplift of 3.05 to 3.3GHz (1.082x) wich is total non sense.

For the maths and, using the numbers displayed in these curves, TSMCs process in this curve has a power/frequency curve of the form P = F^2.28, wich is exactly what we can see on AMD CPUs FI, on the other hand the Intel 7 curve in the segment i mentioned is of the form P = F^7.46 wich is impossible.

What they did is to hugely increase the voltage of the Intel 7 curve at some point, this way they can display an artificial 2x improvement in efficiency.

It’s very relevant for displaying data on the process tech and to provide a proper basis to compare previous nodes. There is no bias in this chart, it’s a technical document. It’s industry standard practice.


Feel free to compare it to similar data released from TSMC & Samsung.

I made the comparison, if ever you understand what it s really all about, Intel curve is worth nothing comparatively to the TSMC one, that s just manipulation for the gullible who dont understand the physics at work.