Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[511]

If I am less pessimistic, I would call the reintroduction of SMT a positive thing, but somehow my gut tells me, this will be at the cost of ST performance gains because time has to be invested into resurrection and hardening to prevent a SpectreV-X. Time that could have gone into the 1T performance. A super wide P-Core or the so called rumored RU is officially a bed time story.

It's majorly in DC though

 

[OneEng2]

For some reason, AMD gets a much bigger boost from SMT than Intel .... which is ironic since Intel introduced it to x86 far before AMD got it.

SMT4 for Intel anyone?

 

[Doug S]

For some reason, AMD gets a much bigger boost from SMT than Intel .... which is ironic since Intel introduced it to x86 far before AMD got it.

SMT4 for Intel anyone?

I was honestly going to suggest the same thing. If you're going to do it, go all the way with it and support SMT4 or even SMT8 like IBM. The additional cost to "go bigger" is less than the cost to do it at all.

I hate on Intel's product segmentation all the time, but it wouldn't make me sad at all if only Xeon and Core i9 type stuff supported SMT, and it was disabled on everything else.

 

[igor_kavinski]

I hate on Intel's product segmentation all the time, but it wouldn't make me sad at all if only Xeon and Core i9 type stuff supported SMT, and it was disabled on everything else.

Just learned few days ago from someone that out of three samples of Alder Lake CPUs with functioning AVX-512 (with mobos that have patched BIOS and microcode), none had issue-free AVX-512 execution. Some cores always error out on some instructions while others work fine. So my speculation is that (like everything else), Intel LIED about hybrid cores as the reason why AVX-512 was disabled in their consumer CPUs. They probably found or were notified of errors too close to launch and then a decision was made to axe AVX-512. Pat was the CEO. Makes me wonder how many other lies he was responsible for.

 

[jpiniero]

Some cores always error out on some instructions while others work fine.

That's kind of what you would expect to happen if an thread just magically moved from a P Core to an E core and tried to do an AVX-512 instruction.

 

[gdansk]

SMT4 for Intel anyone?

It was a punchline but as an ISA's typical workload becomes more and more enterprise-y it seems they trend toward more SMT, not less.

 

[igor_kavinski]

That's kind of what you would expect to happen if an thread just magically moved from a P Core to an E core and tried to do an AVX-512 instruction.

Nope. Even patched BIOS/microcode do not allow enabling AVX-512 with E-cores. The E-cores need to be explicitly disabled for the AVX-512 option to appear in BIOS settings. So the errors are happening with only P-cores enabled. May not matter for something like a PS3 emulator but for anyone actually doing serious work, the errors would've been frustrating. Rather than risk admitting that they messed up, Pat decided to let Intel cover it up.

 

[jpiniero]

Nope. Even patched BIOS/microcode do not allow enabling AVX-512 with E-cores. The E-cores need to be explicitly disabled for the AVX-512 option to appear in BIOS settings. So the errors are happening with only P-cores enabled.

That was the original intention, yes. It's possible that a patch would mess things up, esp if it didn't do things like do the proper voltage adjustments to handle AVX-512.

 

[OneEng2]

It was a punchline but as an ISA's typical workload becomes more and more enterprise-y it seems they trend toward more SMT, not less.

As stated, the only one I can remember doing this was IBM IIRC. I am thinking that you don't get near the boost from SMT4 as you get from nothing to SMT2. ... and you really have to add some serious execution units across the board to do it.

I just wonder if it isn't a better PPA to just add another entire SMT core?