Some wild speculation here. Be gentle.
What do we know.
Cost/transistor has started to increase as node size decreases reversing the previous trend.
Improvements in power, speed are dropping with new node.
TSMC SoIC CoW trails the adoption of a new node by several quarters
Density optimized cache is 2X CPU density
Speculation.
Less processing steps needed for pure cache than CPU die, so even cheaper/transistor.
Putting these together, we can see how designs from AMD and Intel might be diverging.
Traditional way is getting the latest node to stay at the front in the various performance parameters of power, density and cost reduction (no longer true).
Maybe, a different path is now chosen where V-cache and 3D tech allows a better solution.
1)CPU cores are designed traditional way with the cost/transistor now rising slightly. CPU costs increase as even an identical design will cost more at a newer node in spite of the die size falling dramatically.
2)L3 V-cache layers are optimized for density allowing the net total cost/transistor to keep falling relative to designing the combined cores +cache die as one on less dense rules. If 1/2 of your CPU is L3 cache and you can fab it at 2X density, your total silicon area and cost will be 75% of similar transistor count single level design. Assembly, of layers, of course, will eat into that cost saving.
In other words, if you want a CPU to cost X $, you get the highest performance by stacking + optimizing each level with the best libraries for that level, and this works out cheaper (less area and possibly mask steps) than doing everything on one level.
Zen3 was designed before CoW ability was available so it used traditional L3 design for 1st iteration. Future CPUs are designed to use it from the start.
We have seen L3 designed as a concentrated block of cache cells. Is this a design hard wall or a choice based on traditional design? Might we see The entire CPU cores covered by L3 cache with none on the core level? Cache power consumption is relatively low, so is covering the entire cores with L3 cache a problem from a heat dissipation perspective As it might add a few % points to average heat density? Critical hot points would have to accommodated, but this is a small part of your total core area.
Puts some understanding on AMD's statement that they're no longer chasing the newest node at launch. I think we're in store for some amazing products over the next few years.