http://www.xbitlabs.com/news/cpu/display/20050615232538.html
64-bit, DC, memory controllers... Always second...
64-bit, DC, memory controllers... Always second...
Intel is going to integrate Memory controllers on Server chips...
- Thread starter linkgoron
- Start date
Its pretty much a given that it was going to happen sooner or later...
Intel is already R&Ding the whole northbridge integrated onto the CPU. I believe it was backburnered for the Pentium-M/Centrino design though.
Intel is already R&Ding the whole northbridge integrated onto the CPU. I believe it was backburnered for the Pentium-M/Centrino design though.
32-64 : Mee Too
Point To Point Bus : Me Too
On die memory controller : Me Too
NX bit : Me Too
Dual Core: Me Too
Good job there spending a bit more in the future in RnD.
Point To Point Bus : Me Too
On die memory controller : Me Too
NX bit : Me Too
Dual Core: Me Too
Good job there spending a bit more in the future in RnD.
EM64T is AMD64 instructions set. It's only a name change at all. In fact, it's well known that some bug (or whatever it was called) that there was in AMD64 instructions, were found in EM64T too...
EDIT: Here it is (really funny):
http://www.siliconinvestor.com/readmsg.aspx?msgid=20289129
Markfw
Moderator Emeritus, Elite Member
- May 16, 2002
- 27,259
- 16,117
- 136
Yes, when 85% of the cpu's are Intel, and developers write code for it, AMD needs to support it. The other things like integrated memory controllers aren't hacks to an existing core, but base design changes that really enhance performance. Apples and Oranges...
Yeah and I can't believe how awesome those special instruction sets enhance performance. w00t! Intel never did get 3DNow!!
2007...
AMD will have K10 up and running by then, probably with an integrated HTT link to the memory.
It'll be interesting to see just how much benefit Intel will derive from an IMC. It appears that Netburst is more or less maxed out in terms of acheiving its performance potential, since doubling Prescott's L2 to 2MB had little effect.
The Athlon XP was definitely let down by its memory interface, where the P4 already had a far faster memory interface, so I think it's safe to say that Netburst will not benefit from an IMC as much as the Athlon did.
Of course, by 2007, the Xeon may will have ditched the Netburst architecture in favour of another, perhaps Conroe.
AMD will have K10 up and running by then, probably with an integrated HTT link to the memory.
It'll be interesting to see just how much benefit Intel will derive from an IMC. It appears that Netburst is more or less maxed out in terms of acheiving its performance potential, since doubling Prescott's L2 to 2MB had little effect.
The Athlon XP was definitely let down by its memory interface, where the P4 already had a far faster memory interface, so I think it's safe to say that Netburst will not benefit from an IMC as much as the Athlon did.
Of course, by 2007, the Xeon may will have ditched the Netburst architecture in favour of another, perhaps Conroe.
As far as SSE is concerned, AMD brought 3D Now! to the K6, and called it the K6-2. Intel then followed AMD and created SSE for the P2 and called it the P3. Again, Intel followed AMD's innovation.
I'll give you the x86 me-too though.
Intel :
DDR bus : Me too (although they also added their own feature to make it effectively QDR and AMD licensed an Alpha design)
AMD:
pre-Pentium chips: Me too (literally. AMD fabbed copies of Intel chips under license).
Which leads to math coprocessor, floating point unit : Me too
De-coupled architecture (micro-ops) : Me too (Pentium Pro to market before K5)
Just about every process shrink : Me too
On-die L2 cache : Me too (Celeron A before K6-III)
Backside bus : Me too
Writeback cache: Me too
Hyperpipelined architecture : Me too (note: this was when 10 stages was a lot)
MP support : Me too
Dynamic core clock adjustment for notebooks : Me too
(Quite amusingly,...)
Slot design : Me too (even copied the slot to an extent)
Reversion to sockets : Me too
I agree and I cant argue with you, but I just mentioned a few of the tricks that Intel has said "Me too" on the last 16 months or so. Also when you look @ AMD and it's position ( Poor boy) and Intel ( The rich boy) saying " Yes I'll pick a few of your crums too".
Im still in shock from the turn around from Tejas and Nehalem and Ghz rules everything. Being told 32-64 was not worth the effort, that AMD's approach was wrong.
Lets hope there fully awake now, that way I may actaully have trouble deciding which brand of CPU to buy in the next few years instead of " BBQ or athlon".
Rambus is tring to get back with Intel Man I hope its going tobe XDR I well go get the link and post it . Did anyone else read that report at the inquire 2 weeks ago I looked can't find the thread Hay Itanic ondie memory controLLer Maybe Apple O/S for Itanic All 1 year ahead of my time frame. Pinch me Iam dreaming. Apple servers ??? Remind me to never get Intel angry. 65 nano tech less leakage than antisapated I have never seen David so gidi in my life. He wants it to be XDR so bad. 8mb catch oh oh oh this is so cool. I have to go see Zinn2b's post . I know he's going nuts. Guys not tring to be smart arse but zinn is looking like a genious . I know he is seeing $$$$$ signs. I go check him out.
More breaking news Zinn has backed off he is just so pleased how everything has turned out . He seems to be at peace with himself. Good for him . Gee it just gets better and better
More breaking news Zinn has backed off he is just so pleased how everything has turned out . He seems to be at peace with himself. Good for him . Gee it just gets better and better
If they bought AMD, companies like IBM, TSMC, and transmeta would pretty much instantly sue for antitrust. Intel needs AMD.
trying
will
inquirer
giddy
cache
trying
genius
Edit: and im not one of those "spelling police" type people, you dont even try to make sense, we have to reread your post 6 or 7 times just to try get what youre trying to convey. We then have to go through and filter out the drivel just to figure out what the hell you are trying to say.
Many of us want it to be XDR over DDRII/III. There are definately many advantages.
There is no talk of Itanium being adopted by apple, they are looking at X-86 cpus only for now, not IA64.
I have heard nothing, anywhere, about Intel reporting "less leakage than expected" in regards to 65nm technology.
Also, I have no friggin idea who Zinn is.
They havent said anything officially but the TDPs of their up and coming .65nm chips have dropped off considerably. I take it as a good sign
But seriously, it's IBM that has excellent 65nm process that has much less leakage.
I doubt that IBM license it to Intel, but for AMD they probably will.
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