Intel Investor Meeting 2017: February 9

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ShintaiDK

Lifer
Apr 22, 2012
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Exactly. Intel realizes the threat that TSMC and the ARM ecosystem along with AMD/GF poses to its cash cow DCG. Intel's 10nm and TSMC 7nm / GF 7nm are for all intents and purposes going to be competing in the same time frame when it comes to server products. Intel realizes that it cannot drag its feet going forward as there are hungry competitors who will move to the bleeding edge nodes at the earliest possible time. Intel is just acknowledging that their past methods will not work going forward.

Unicorns and fairy tales again?
 
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Mar 10, 2006
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Exactly. Intel realizes the threat that TSMC and the ARM ecosystem along with AMD/GF poses to its cash cow DCG. Intel's 10nm and TSMC 7nm / GF 7nm are for all intents and purposes going to be competing in the same time frame when it comes to server products. Intel realizes that it cannot drag its feet going forward as there are hungry competitors who will move to the bleeding edge nodes at the earliest possible time. Intel is just acknowledging that their past methods will not work going forward.

Well they are going to take a margin hit to do this, which is why Intel stock took a hit. But long term it is the right thing to do, better to have slightly lower margins due to being aggressive on process than to lose sales.
 

raghu78

Diamond Member
Aug 23, 2012
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Arachnotronic Intel's change of tactics is a forced one and basically acknowledges that there is serious competition coming at them from both AMD and the likes of Qualcomm and other ARM designers. All these companies will move to bleeding edge nodes at the earliest possible timeframe. The big problem for Intel is their process leadership is basically gone. Apple is bankrolling TSMC's rapid march to 7nm and 5nm. GF with the help of IBM is capable of staying close behind Intel / TSMC. We will see Intel 10nm server chips and TSMC 7nm based Qualcomm server chips along with GF 7nm based AMD server chips in 2019. If Intel were to stick with their old model of 18 month lag in moving server CPUs to the latest nodes that could pose serious problems as their competitors keep moving to the latest TSMC and GF nodes as they are available.

The question I think Intel needs to answer is how are they going to yield massive dies at 7nm if they are going first to server. I think the first generation chips are going to be shrinks with no major core count increases. So if Intel have a 10nm++ chip at 500 - 600 sq mm then at 7nm it should be around 300 sq mm. That would allow them to yield well and use the learning to ramp up die sizes in the second and third iterations.
 
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witeken

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Dec 25, 2013
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Doug Davis : IoT and ADAS
TL;DR:

*Forecasts stable double digit growth far into the future and MSS growth

*ADAS = important

*Collabing with FPGA, 5G and data center

  • MSS = 14%, grown faster than market last ~7 years
  • Focused on high-value 32-bit computing, the lower-bit has actually contracted in last ~7 years
  • Focused on gateways, then connecting to network and data center (smart + connected + software defined + analytics)
  • Expect 12% CAGR through 21, but Intel expects to grow faster than market
  • Wind River. Many opportunities in various markets (insert busy slide of critical techs, standards, silicon, memory, IP, software, M&As, patners)
  • Retail: 7B ‘21 SAM
  • Industrial: 8B ’21 SAM
  • Video: 6B ‘21 SAM, from analog to higher resolution smart cameras
  • ADAS: today Intel has an addressable Silicon BOM of $100-200 in car, will grow 10-15x (=10B TAM in 2025). Everyone knows the story: autos will need FPGA, Xeons, etc. Announced end-to-end Go brand at CES. Working together with data center group.
  • = 32B Si SAM opportunity ‘21


Next up: Bob Swan (CFO)!

Will there be a Haiku???
 

witeken

Diamond Member
Dec 25, 2013
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What are you saying? In the last thread where we had a discussion, I told you to expect Intel to move DCG/HEDT to leadership on nodes, and you vehemently disagreed with me telling name that they need to do small dies first.

Intel said at the conference that DCG product node leadership will begin with 10nm++, not 7nm.

This fits the roadmap that mikk showed us on this forum. Ice Lake-EP will possibly be out on 10nm++ in 2019 and Sapphire Rapid on 7nm in 2020.
7nm DCG in 2020 would be unreal!
 
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liahos1

Senior member
Aug 28, 2013
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DCG subsegments like omnipath and ethernet is also expected to grow faster than the cpu segment through 2021. Perhaps as these products are smaller scale the operating margins are lower...I'd expect as these products scale for operating margin to scale and reduce the drag they are expected to have
 

witeken

Diamond Member
Dec 25, 2013
3,899
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Bob Swan : Financials

TL;DR:
*Self-introduction of new CFO

*Official confirmation of Soft Machines acquisition. #VISC

  • IDM advantage, Moore’s Law leadership, and innovative products
  • CCG = stable. 14-16: 15% volume down, but only 3% CAGR decline
  • DCG = growth into the future (high single digit)
  • IoT = leverage existing IP to reach new, vertical markets (>10%)
  • NAND (>20% growth ’17)
  • FGPA (mid-single digit)
  • Slide of how spending in 2016 changes to 2017F. Spending declines in security and CCG, increasing in the 3 growth segments, and also a little increase in Moore’s Law as always
  • Reiterates the word data. And I thought big data was the buzzword of 2013!
  • Intel knows we question Moore’s Law lead and other things.
  • Lots of recap of tech.
  • Capex goes up a lot, driven by memory mainly, which is now category for Intel. But capex for logic as percent of revenue is stable.
  • R&D spending aligned with TAM growth, but targeting higher effiency
  • M&A: Altera recap, took slide from the announcement in 2015 and evaluate the statements made (3 positive checks) = good acquisition.
  • Confirmation of Soft Machines M&A
  • Dividend increase (to be approved by BoD) and plan to grow in line with non-GAAP EPS growth, which will be slightly higher than operating income growth, which will be slightly higher than revenue growth.
  • Over next 3 years: expect low-single digit revenue growth


Next up: Q&A!
 

CatMerc

Golden Member
Jul 16, 2016
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https://videocardz.com/65800/intel-promises-more-than-15-better-performance-for-intel-i7-8000

During its annual investors day, Intel shed some light on upcoming Cannonlake architecture. The company promises over 15 percent better performance compared to Kabylake. While no exact numbers were shared, it was told that they are based on SysMark benchmark.

More importantly, Intel Cannonlake is currently expected to ship in the second half of 2017. This probably means entry-level parts with faster CPUs coming at a later date.

It’s also worth noting that the slide below is clearly comparing i7 series, a direct competitor to AMD Ryzen, which is expected to launch later this month.

Considering what Kaby Lake brought to the table, and considering 8th Gen is a tick , I imagine it's 15% better performance under a limited power envelope. Kaby Lake did the same for CPU's under 35W/15W. 8700K is probably not much better than Kaby Lake was from Skylake.
 

witeken

Diamond Member
Dec 25, 2013
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Q&A
TL;DR:

*Some questions (e.g. some finance ones) I did not find interesting are omitted.

*Confirms that 3DXP did not meet target time to market (Skylake Xeon).

*Boring questions? Boring answers?

  • DCG margins? CPU = very high margins, so as adjacencies become bigger, margins go down. Also, because DCG goes to leading edge first, it has higher wafer cost and takes a bigger burden of R&D on its name.
  • Investing in neuromorphic and quantum computing too
  • Needs to invest in some current transitions in the industry NOW like 5G and rack-scale, not later to hit some operating margin.
  • Still shipping first 10nm in 2017, but volume in 2018. But also fairly big inter-node improvements.
  • Foundry: not general-purpose, but things like low-power high performance and FPGA.
  • Is Intel growth company? If Intel does not invest and solely gives back to investor, will fall behind and lose Moore’s Law leadership. Needs to grow to feed Moore’s Law and afford those factories.
  • Xeon+FPGA integrated solution is sent to customers to let them figure out use case, will go into production this year. Xeon Phi is increasingly being used.
  • Silicon photonics 16 year investment. But delayed by a year. 3DXP also 10+ year, was targeted to make it for the Skylake launch, but will ramp in 2018.

Alright folks, that's it for today. A few interesting tidbits for sure. The highlights are in the TL;DRs and my tweets.
 

Dresdenboy

Golden Member
Jul 28, 2003
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citavia.blog.de
DCG margins? CPU = very high margins, so as adjacencies become bigger, margins go down. Also, because DCG goes to leading edge first, it has higher wafer cost and takes a bigger burden of R&D on its name.
So another group is going to look much better with wafer costs and R&D reduced there...
 
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witeken

Diamond Member
Dec 25, 2013
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Arachnotronic Intel's change of tactics is a forced one and basically acknowledges that there is serious competition coming at them from both AMD and the likes of Qualcomm and other ARM designers.
Intel has never denied competition. Secondly, it makes a thousand times more sense for a company to put its growing businesses on the leading edge than a stagnant, albeit big, one.
 
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Mar 10, 2006
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Arachnotronic Intel's change of tactics is a forced one and basically acknowledges that there is serious competition coming at them from both AMD and the likes of Qualcomm and other ARM designers. All these companies will move to bleeding edge nodes at the earliest possible timeframe. The big problem for Intel is their process leadership is basically gone. Apple is bankrolling TSMC's rapid march to 7nm and 5nm. GF with the help of IBM is capable of staying close behind Intel / TSMC. We will see Intel 10nm server chips and TSMC 7nm based Qualcomm server chips along with GF 7nm based AMD server chips in 2019. If Intel were to stick with their old model of 18 month lag in moving server CPUs to the latest nodes that could pose serious problems as their competitors keep moving to the latest TSMC and GF nodes as they are available.

The question I think Intel needs to answer is how are they going to yield massive dies at 7nm if they are going first to server. I think the first generation chips are going to be shrinks with no major core count increases. So if Intel have a 10nm++ chip at 500 - 600 sq mm then at 7nm it should be around 300 sq mm. That would allow them to yield well and use the learning to ramp up die sizes in the second and third iterations.

They aren't going to need to yield massive dies. They are going to "chop up" the dies and stitch them back together using EMIB packaging. Intel says that it will be virtually indistinguishable from a monolithic die, none of the issues associated with traditional MCM.

Amazing technology, maybe you now have your answer about what Intel has been doing for all these years.

The EMIB tech is key to Intel's new "data center first" strategy.
 
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witeken

Diamond Member
Dec 25, 2013
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So another group is going to look much better with wafer costs and R&D reduced there...
Yeah, as Swan said it's a zero sum game. In the past the losses went to mobile ("Intel wasted $10B in mobile", which is a big exaggeration), now they're going to DCG.
 

CatMerc

Golden Member
Jul 16, 2016
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They aren't going to need to yield massive dies. They are going to "chop up" the dies and stitch them back together using EMIB packaging. Intel says that it will be virtually indistinguishable from a monolithic die, none of the issues associated with traditional MCM.

Amazing technology, maybe you now have your answer about what Intel has been doing for all these years.

The EMIB tech is key to Intel's new "data center first" strategy.
Explain the benefits of EMIB vs MCM?

First I'm hearing of EMIB, sounds interesting.
 

witeken

Diamond Member
Dec 25, 2013
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Explain the benefits of EMIB vs MCM?

First I'm hearing of EMIB, sounds interesting.
EMIB aka 2.5D is Intel's solution for 3D integration. The interposer tech that for instance AMD has used for HBM is expensive. Intel's solution is as cheap as possible, but has same advantages. You use it to basically create a giant die by 3D stacking / connecting.

http://semiengineering.com/one-on-one-mark-bohr/
http://semiengineering.com/deeper-inside-intel/

But I don't know how it stacks up versus regular MCM, or put another way what the disadvantage of e.g. AMD's 32-core server MCP will be versus monolithic die. I suppose EMIB just allows you to chop it up and treat it as a single monolithic die for all intents and purposes.
 

CatMerc

Golden Member
Jul 16, 2016
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http://www.intel.com/content/www/us/en/foundry/emib.html

Check this out, it's like interposers on steroids and without the limitations :)
Looks pretty damn great for creating very large CPU's. If for example AMD were to create a 6-8 die Naples CPU, they would probably have to use technology like this.

However compared to an MCM, it's probably not much better as long as the total die size of all the chips isn't too large to manufacture an interposer for.
 
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jpiniero

Lifer
Oct 1, 2010
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So let me get this straight:

10 nm: Cannonlake (U/Y only) and Coffee Lake on 14 nm
10 nm+: Cannonlake-X (but no EP) then Icelake
10 nm++: Icelake-EP/X then Tigerlake
7 nm: Sapphire Rapid?