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Intel hires former AMD Marketing Director Chris Hook

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I was listening to the TSLA earnings call and something interesting came up. An analyst asked Elon Musk "We heard that Jim Keller was departing from Tesla. What does his departure say about the state of your custom SoC development?"

Elon Musk says "Well, Jim is a great guy. He is very good with designing architectures and he has always dreamt about redesigning the server architecture of a CPU. The opportunity arose for him to purse that desire, so he will be leaving to go design a new server architecture at Intel"


So apparently Jim Keller will be designing the next new server architecture at intel. It makes a lot of sense that they would try to compete in their highest margin business (Xeon) against AMD's Epyc. They will need all the help hey can get if the rumors about 7nm Epyc are true (256MB L3)
 
FIVR said:
They will need all the help hey can get if the rumors about 7nm Epyc are true (256MB L3)
Click to expand...

I wouldn't believe that. It would be too slow/expensive. If anything it would probably make more sense to do a 32MB L3 and 128MB L4. Cache is supposed to be pyramid-like anyway.

Also there were (stupid) rumors the first Epyc would have 512MB L3.
 
FIVR said:
I was listening to the TSLA earnings call and something interesting came up. An analyst asked Elon Musk "We heard that Jim Keller was departing from Tesla. What does his departure say about the state of your custom SoC development?"

Elon Musk says "Well, Jim is a great guy. He is very good with designing architectures and he has always dreamt about redesigning the server architecture of a CPU. The opportunity arose for him to purse that desire, so he will be leaving to go design a new server architecture at Intel"


So apparently Jim Keller will be designing the next new server architecture at intel. It makes a lot of sense that they would try to compete in their highest margin business (Xeon) against AMD's Epyc. They will need all the help hey can get if the rumors about 7nm Epyc are true (256MB L3)
Click to expand...
Good find.
 
Thunder 57 said:
I wouldn't believe that. It would be too slow/expensive. If anything it would probably make more sense to do a 32MB L3 and 128MB L4. Cache is supposed to be pyramid-like anyway.

Also there were (stupid) rumors the first Epyc would have 512MB L3.
Click to expand...
Doubling of L3 per core isn't that big of a stretch (EPYC 2 is rumored to have 64 cores), considering 7nm SRAM density is damn insane.
 
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witeken said:
Epyc 2 is likely 48 cores.
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CPCHardware can be trusted with claims like that. If they said 64 cores I'd say it's 64 cores.

I expect there to be two dies, one Tri-CCX and another Quad-CCX. Tri-CCX die optimized for single threaded performance while the Quad-CCX die is optimized for density/efficiency.
 
CatMerc said:
I expect there to be two dies, one Tri-CCX and another Quad-CCX. Tri-CCX die optimized for single threaded performance while the Quad-CCX die is optimized for density/efficiency.
Click to expand...

At this point I don't think AMD has the capacity to do something like that. It's going to be one die that's reused like how Ryzen/Threadripper/Epyc is today.
 
jpiniero said:
At this point I don't think AMD has the capacity to do something like that. It's going to be one die that's reused like how Ryzen/Threadripper/Epyc is today.
Click to expand...

AMD probably did not have the resources back in 2014-2015 when the Zen core was being designed. But AMD is already going with a dedicated compute GPU at 7nm with compute specific features in 7nm Vega and 7nm Navi optimized for gaming. I still think the effort to validate to separate CPU cores using different libraries is huge. So I am waiting to see what AMD has done here.
 
CatMerc said:
CPCHardware can be trusted with claims like that. If they said 64 cores I'd say it's 64 cores.

I expect there to be two dies, one Tri-CCX and another Quad-CCX. Tri-CCX die optimized for single threaded performance while the Quad-CCX die is optimized for density/efficiency.
Click to expand...
So just like an alternative to big.LITTLE concept ?
 
CatMerc said:
Doubling of L3 per core isn't that big of a stretch (EPYC 2 is rumored to have 64 cores), considering 7nm SRAM density is damn insane.
Click to expand...

Yes, but how would they arrange that cache? A giant L3? A smaller non-inclusive L3 with a giant L4? That would result in a whole lot of snooping L2's. An inclusive L3 with a somewhat smaller L4 as LLC? I am curious to see what they do with the extra die space.
 
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wahdangun said:
So just like an alternative to big.LITTLE concept ?
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No. Just one die with 12 cores and another with 16 cores.

jpiniero said:
At this point I don't think AMD has the capacity to do something like that. It's going to be one die that's reused like how Ryzen/Threadripper/Epyc is today.
Click to expand...
AMD's R&D budget is growing and fast. They can do it.

I expect the 16 core die to be exclusivey used in EPYC, while the 12 core die is used in desktop/threadripper/lower core count EPYC.

The 16 core one will likely have a DDR5 memory controller while the 12 core will have a DDR4 controller. The 16 core one will likely also support PCI-E 4.0, which is a stop gap since PCI-E 5.0 is coming really soon.
 
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CatMerc said:
No. Just one die with 12 cores and another with 16 cores.


AMD's R&D budget is growing and fast. They can do it.

I expect the 16 core die to be exclusivey used in EPYC, while the 12 core die is used in desktop/threadripper/lower core count EPYC.

The 16 core one will likely have a DDR5 memory controller while the 12 core will have a DDR4 controller.
Click to expand...


but by concept isn't that big.little ? i mean big core/die paired with little core/die, but its used for maximum performance instead of energy efficiency. and the os need to aware what core to be used by application based on how much the core is used thread ?
 
wahdangun said:
but by concept isn't that big.little ? i mean big core/die paired with little core/die, but its used for maximum performance instead of energy efficiency. and the os need to aware what core to be used by application based on how much the core is used thread ?
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They wouldn't be paired for one, only with each other of the same die.
 
Bondrewd said:
They *need* a dedicated server die to pander to hyperscale.

Waaaaaaaay too early.
Maybe something Zen5-based (assuming they skip number 4).

Vega20 already has is, so I'd expect anything else AMD to support it too.
Maybe.
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First DDR5 devices are expected in 2019. This isn't too early.
 
CatMerc said:
I expect the 16 core die to be exclusivey used in EPYC, while the 12 core die is used in desktop/threadripper/lower core count EPYC.

The 16 core one will likely have a DDR5 memory controller while the 12 core will have a DDR4 controller. The 16 core one will likely also support PCI-E 4.0, which is a stop gap since PCI-E 5.0 is coming really soon.
Click to expand...

I don't see how this is practical. What do you do with defective DDR5 dies? And you would need an entirely new socket for it.
 
CatMerc said:
A lot of software is licensed per core. Having a higher perf/core die for those makes perfect sense.
Click to expand...

So you sell them less cores with higher clocks from a defective 16 core die.

Now a high frequency optimized die would make sense, but it's too small of a market for AMD to make a native die for given their resources, and it would have to be much higher than what the base die could achieve.
 
CatMerc said:
First DDR5 devices are expected in 2019.
Click to expand...
i_believe_it_when_i_see_it.png
Cadence has JUST shown working DDR5 IP.
jpiniero said:
Having both at the same time makes no sense.
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Why? One die for plebs, another for big boys.
jpiniero said:
Now a high frequency optimized die would make sense, but it's too small of a market for AMD to make a native die for given their resources
Click to expand...
Their current growth is mostly client revenue, EPYC is yet to become relevant.
A dedicated high-clocking consumer die is pretty much given.
 
jpiniero said:
So you sell them less cores with higher clocks from a defective 16 core die.

Now a high frequency optimized die would make sense, but it's too small of a market for AMD to make a native die for given their resources, and it would have to be much higher than what the base die could achieve.
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How do you intend to clock higher a design that isn't built to clock higher?

It's not too small a market, it's a large market that is yet another growth potential for them, AND it doubles up as higher strength in HEDT and consumer.

As an Intel employee once put it, AMD could live like kings if they had the revenue that just HEDT generates.
 
Is AMD upping it's die sizes for Zen2 based EPYC CPUs? Double the L3$/core plus (I'm guessing) 256bit AVX2 plus other core improvements for higher IPC would mean a bigger die size even with the node shrink (for quad CCX based designs). I'm more inclined to believe that AMD is going with a triple CCX based design with more L3$ and other improvements for good yields and more reasonable TDPs.
 
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