Question Intel had a 7 GHz CPU years ago

[igor_kavinski]

https://www.reddit.com/r/hardware/comments/wir8ay

213 mm2 die size, 150 Watts, 50 pipeline stages all for one core at >7 GHz.

I'm getting a strong feeling of lust for this CPU. 150W ain't that much. Imagine what this CPU could have been if it had been developed further, with modern branch predictors and huge caches.

 

[igor_kavinski]

At this point I think I'd rather bang my head against the wall than discuss this anymore. You know what they say when you think you are right even everyone else tells you that you're wrong. You're wrong.

It's not about right or wrong. P4 was a baby killed too soon. It could've grown and become a beautiful swan.

You are only thinking of the P4 design being static and not evolving. That's not how CPUs evolve. They get better with each iterative design.

 

[igor_kavinski]

I believe Intel may never revisit P4 because they like to think they are too wise (explains their current predicament). I think a better outcome would be selling the design to china and let them iterate on it. I would certainly buy it if I were a billionaire.

 

[RTX]

Some fancy rumors that I hoped would come true with Prescott. It was in a post in a website named geek.com or something. It was very active until it got disbanded.

-Hyperthreading 2
-3 decode
-16-24K uops Trace Cache(2-3x Northwood)
-Enhanced branch prediction

Back then there were nothing about extended pipeline stages. When I saw Intel presentation about 31 stages, my heart sank. Actually, if they kept the above specs without the extended stages, Prescott would have been significantly faster per clock. Of course the 3 decode was just a rumor.

Also, despite Nosta's fantasy about FD-SOI, 22nm Tri-Gate/FinFET transistor achieves most of the FD-SOI effects while improving gate control. That's because if you look at the picture, the "Tri-Gate" has only one thin side that's contacting the substrate.

Planar vs Trigate: https://www.tel.co.jp/museum/magazine/material/150227_report04_01/img/img_report04_03.jpg
FD-SOI vs Trigate: https://www.hardware.fr/medias/photos_news/00/32/IMG0032086_1.jpg

Thus, it achieves most of the effects of SOI without needing the extremely thin layer, while offering other benefits like improved gate control. GAA completes the transition, because instead of 3 sides surrounding the gate, it's surrounded by all 4 sides.

Did the team have ideas to fix that arch?

 

[LightningDust]

I'm really sorry, your Majesty, that a little disagreement or opinion interferes with the peace you would otherwise have experienced carrying out your daily routine of dusting your old Itanium server (sorry not sorry).

My daily routine is actually in working in the semi industry, not writing poorly-informed fanfiction about it.

 

[igor_kavinski]

poorly-informed fanfiction

Try not to be jealous of my writing skills

 

[NTMBK]

I liked the 865G. The Extreme Graphics 2 in 865G was twice the performance of 845G, even though it kept the 1 pipe/2 TMU config. It was probably the fastest 1 pipe/2 TMU graphics ever made.

I mean sure, that's pretty cool, but what if you shrunk it to 3nm and clocked it at 10GHz

 

[Doug S]

It's not about right or wrong. P4 was a baby killed too soon. It could've grown and become a beautiful swan.

You are only thinking of the P4 design being static and not evolving. That's not how CPUs evolve. They get better with each iterative design.

You are literally the ONLY person I've ever heard defending P4. It was never going to be a swan, it was always a platypus.

 

[Jan Olšan]

Platypus is extremely intersting tho. As is Netburst.

 

[naukkis]

You are literally the ONLY person I've ever heard defending P4. It was never going to be a swan, it was always a platypus.

Willamette/Northwood were extremely performance oriented cores. They still can have best IPC of any core in some latency sensitive codepaths. Transistor density of that time didn't allow them to really support that performance resulting design that didn't really perform - but if someone would really do well performing x86 design it would be more like P4 than Royal core. Intel of course is totally lost with their designs - for Royal core they should have use ISA to support that kind of cpu design and for x86 they should bring P4 design team back.

 

[Hitman928]

Dawg, Power6 shipped in commercial volumes at 5.0GHz on 65nm, and it did it while being able to sustain decode, issue, and execution of four instructions per cycle, not Pentium4's measly single instruction.

"It overclocked to 4.6, ergo it wasn't a completely broken microarchitectural concept" is certainly a take. But hey, I'm remembering why I stopped posting here.

Your posts are appreciated here Ana I understand the frustration. Just got to learn not to get down in the mud with some posters or utilize the ignore button if all else fails

 

[DavidC1]

Because DavidC1 likes saying how efficient and performant Atoms are compared to P4.

Because it is?

At the end of the day, you are limited by transistor count, which turns to die area and power. The Atom architectures are FAR better at extracting that than any P cores, including the P4.

Also you are telling me, a 130W desktop chip needs substantial overclocking in order to barely beat a 6W notebook chip? At 4.68GHz, that P4 would use close to 200W. So it's 200W vs 6W for roughly similar performance. Great argument man. And 14nm wouldn't close that gap enough. It would still be far far away.

Did the team have ideas to fix that arch?

Obviously not, because they went on to create Tejas, which had 50+ pipeline stages and wanted to reach 10GHz with it. But then Prescott wanted to reach 7GHz too, and it couldn't get to 4GHz.

I don't know why you have this what-if obsession with Tejas. The only period where I remember than the P4 was really good was with Northwood C, the ones with 800 MHz Bus and Hyper Threading were quite above the Athlon XPs, albeit that came at a BIG price premium.

Northwood sucked too. If you remember the 2.2GHz Northwood review, it was 3-5% faster than Willamette and clocked 10% higher, which beat out the competing Athlons. Yes, it did better in some corner case scenarios where Willamette sucked, but we're talking 1 in 10 applications. Northwood was viewed in a very positive light because it allowed the clocks to ramp faster due to 0.13u process too. And AMD couldn't scale as high, and their vaunted 0.18u copper underperformed Intel's 0.18u alu process by a substantial amount.

This was my reaction to showing my friend that Intel is beating AMD with Northwood: "That's it? It's like 5%" Which was true...

For all practical reasons, the actual question here is why Intel prefered the Prescott oven instead of a simple Northwood shrink to 90nm.

Prescott's design would have been much better, if they did not add the 31 stage pipeline, which was 11 more than the troubled 20 stage on Willy/North. Without it, it would have performed 10-20% better easily, and 30%-plus in some applications. It would have likely used less power too. But why iterate on a half-dead design when you can start fresh?

Competent architecture work requires a lot fewer of them. Fact is, Netburst designs were barely competitive - against K8, Power, or IPF - and often lost on single-threaded perf to contemporary Pentium M running at drastically lower clock.

😅😂🤣

Yes, if Intel continued with P4, then Itanium would have been adopted. Itanium was ~2x faster per clock. Itanium's coffin was sealed shut when a much lower power and higher clocking architecture performed similarly - Core 2.

 

[igor_kavinski]

Itanium's coffin was sealed shut when a much lower power and higher clocking architecture performed similarly - Core 2.

Core was the stupid architecture that led to Intel's complacency and almost a decade of four crappy cores from Nehalem to Kaby Lake.

Just admit it. Core turned out to be Intel's worst mistake. It should not have lasted more than five years. Together with 14nm, Core architecture was responsible for getting Intel into its current mess.

Intel's great architectures were Ice Lake and Tiger Lake and Rocket Lake would've been too if it hadn't been manufactured on 14nm. Then Intel screwed the pooch with the large Golden Cove core that used too much power compared to Ryzen. The Core team has been nothing but a phenomenal failure in terms of architecture design that couldn't iterate successfully and just kept adding bloat.

 

[Thunder 57]

Because it is?

At the end of the day, you are limited by transistor count, which turns to die area and power. The Atom architectures are FAR better at extracting that than any P cores, including the P4.

Also you are telling me, a 130W desktop chip needs substantial overclocking in order to barely beat a 6W notebook chip? At 4.68GHz, that P4 would use close to 200W. So it's 200W vs 6W for roughly similar performance. Great argument man. And 14nm wouldn't close that gap enough. It would still be far far away.

Obviously not, because they went on to create Tejas, which had 50+ pipeline stages and wanted to reach 10GHz with it. But then Prescott wanted to reach 7GHz too, and it couldn't get to 4GHz.

Northwood sucked too. If you remember the 2.2GHz Northwood review, it was 3-5% faster than Willamette and clocked 10% higher, which beat out the competing Athlons. Yes, it did better in some corner case scenarios where Willamette sucked, but we're talking 1 in 10 applications. Northwood was viewed in a very positive light because it allowed the clocks to ramp faster due to 0.13u process too. And AMD couldn't scale as high, and their vaunted 0.18u copper underperformed Intel's 0.18u alu process by a substantial amount.

This was my reaction to showing my friend that Intel is beating AMD with Northwood: "That's it? It's like 5%" Which was true...

Prescott's design would have been much better, if they did not add the 31 stage pipeline, which was 11 more than the troubled 20 stage on Willy/North. Without it, it would have performed 10-20% better easily, and 30%-plus in some applications. It would have likely used less power too. But why iterate on a half-dead design when you can start fresh?

😅😂🤣

Yes, if Intel continued with P4, then Itanium would have been adopted. Itanium was ~2x faster per clock. Itanium's coffin was sealed shut when a much lower power and higher clocking architecture performed similarly - Core 2.

Pretty sure it has been accepted K8 killed Itanium. 64 bit backward support with excellent performance. Pretty much a no brainer rather than IA-64 with slow x86 emulation.