Intel first to demonstrate working 45nm chip's..

[TuxDave]

Originally posted by: mxzrider2

Originally posted by: dmens
Again, process comparisons are totally meaningless if you baseline it with different designs. For example, I can make yonah draw 3-4x more power than in commercial operation by messing with some debug features. Going by your reasoning, I can take yonah-in-debug and claim 65nm sucks ass compared to dothan at 90nm.... but that comparison is obviously garbage.

dude that doesnt matter what is being said is that intel processors at 65nm stil take more power than amd procs at 90 nm. learn to read even though this is a generazation as you are correct that dothan ( SOME) does consume less power than almost all amd procs( current) cept maybe those geo ones or what ever.

But what can you infer about the process technology when comparing a 65nm presler vs a 90nm A64? Not much.

 

[BrownTown]

I have been working with the 45nm Intel process and it certainly is a departure in a number of signifcant ways from previous process technologies although I'm not sure if I'd characterize it as the biggest change since the 60's. I also don't know if it will "make or break Intel" - it seems unlikely that anyone would let the company be put in a situation where this is the case - and it also remains to be seen what everyone else is going to do on 45nm. But, yeah, I agree with you fundamentally... 45nm is going to be very different.

Well, i don't think it will be the biggest change since 1960 either, but thats what Intels marketing said. Also, I didn't mean that it would make or break intel as a company, only that it would be very decisive in how their company performs in 2008. Also, maybe if you've worked on the 45nm maybe you can clear some things up about it. I've still heard some confusion as to whether or not it will be using FD-SOI, high-k, tri-gate transistors, or those metal interrconects. I believe these are all things that were considered for this processes, but did they actually make the cut?

 

[dmens]

maybe you can clear some things up about it

I asked about the nitty gritty details at the tech intro and got dirty looks from the presenter.

 

[coldpower27]

Originally posted by: Viditor
Well, Hector Ruiz stated those facts at a Conference call...which means if he's lying he can go to prison. The article you linked isn't even quoting anyone specific about the Intel yields, and certainly nobody in senior management (who could be held liable).
So, please forgive me if I remain dubious as to the articles claims...

Which conference call did Hector Ruiz make such statements?

 

[stardrek]

Originally posted by: BrownTown

I have been working with the 45nm Intel process and it certainly is a departure in a number of signifcant ways from previous process technologies although I'm not sure if I'd characterize it as the biggest change since the 60's. I also don't know if it will "make or break Intel" - it seems unlikely that anyone would let the company be put in a situation where this is the case - and it also remains to be seen what everyone else is going to do on 45nm. But, yeah, I agree with you fundamentally... 45nm is going to be very different.

Well, i don't think it will be the biggest change since 1960 either, but thats what Intels marketing said. Also, I didn't mean that it would make or break intel as a company, only that it would be very decisive in how their company performs in 2008. Also, maybe if you've worked on the 45nm maybe you can clear some things up about it. I've still heard some confusion as to whether or not it will be using FD-SOI, high-k, tri-gate transistors, or those metal interrconects. I believe these are all things that were considered for this processes, but did they actually make the cut?

This is taken off of Intel's website. Here: http://www.intel.com/technology/silicon/si11031.htm

"High-k/metal gate is a technology option for replacing the silicon dioxide/polysilicon gate in Intel's 45nm logic technology process. That process is on track for 2007 production and is consistent with the company's 2-year Moore's Law cycle."

 

[BrownTown]

yeah, i've read that press release (it the one withthe 1960s reference), but I'd rather see some confirmation that the 45nm process we are currently seeing be demonstrated is in fact using all these technologies. But i've heard alot of speculation that the 45nm technology we are currently seeing still inculdes all those innovations. Certianly the 5x less leakage would indicate that the high-k could be working. However, others like IBM and AMD have stated that they do not think high-k is a good idea, while others say that they doubt Intels ability to bring all these to market at the 45nm node.

Also, do you know when that was released?, if it was 2 years ago (like it appears to be) then things could drastically have changed...

 

[Viditor]

Originally posted by: pm

Originally posted by: BrownTown
From what I've read about Intel's process for the 45nm node it sounds like its gonna be very different than their last few revisions. They claim its the most revolutionary process since the 1960's. Anyways, whether or not it works could really make or break Intel in 2008.

I have been working with the 45nm Intel process and it certainly is a departure in a number of signifcant ways from previous process technologies although I'm not sure if I'd characterize it as the biggest change since the 60's. I also don't know if it will "make or break Intel" - it seems unlikely that anyone would let the company be put in a situation where this is the case - and it also remains to be seen what everyone else is going to do on 45nm. But, yeah, I agree with you fundamentally... 45nm is going to be very different.

Originally posted by: Viditor
I wouldn't be so sure...just because Intel came out with the process sooner, doesn't mean they had those cost advantages from the smaller die right away. It's most likely that initial yields (at least the first 2 turns...6 months) had very poor yields (this is SOP). Remember that Intel absolutely HAD to convert when they did because they were about to hit a speed wall with Northwood.
Your point on SOI is quite valid though...
All in all, I'd bet (don't know for sure) that Intel's 90nm transition (and probably their 65nm transition) will create chips that are more expensive than their previos nodes...at least for the first 6-9 months.

I'm not sure that I would say that "very poor yields" initially is SOP - at least not at Intel, nor any other high volume manufacturer. Typically, a process is not "deployed" until the yields hit a certain internal goal and knowing this number, I don't think that anyone would ever declare it to be "very poor". Often yield is usually a function of speed or leakage... so by pulling back on speed, you can improve yield. So if your newly deployed process is yielding poorly, the first thing that takes the hit is speed bin. This is not always the case, but it's very common.

The process is usually pretty thoroughly checked out well in advance of shipping - bear in mind that parts sample on a new process years before that process is relied upon for HVM - for example, we are seeing 45nm working IC's today years ahead of their release. Back-end validation (all the stuff that happens between A0 tape-out and final release) takes many quarters... there is plenty of time to tweak yields. A product will not release unless yields are above a set goal - release will be delayed if this is a concern. Normally a part that doesn't yield well is also far more likely to have reliability problems in the field - no one in high-volume manufacturing wants to take a hit with customers (either OEM's or end customers) for high failure rates in the field. So, to summarize, I disagree that "very poor yields" is standard operating procedure on products shipping on a new process.



As far as the discussion of who's process is lower power... you need to, as several people pointed out - compare apples to apples. Comparing microprocessor TDP is not the way to do this. The way that people should be doing this comparison is to pull the trade journal articles (IEEE IEDM articles) for the years when companies are disclosing process information and then look and see what Intel and AMD have for Ion/Ioff ratios for NMOS and PMOS FETs. To my recollection AMD does not usually disclose numbers at this conference, but with the collaboration between IBM and AMD, the IBM numbers should work as a general estimate. I don't have the time, or the motivation to do this, but arguing TDP definitions vs. microarchitectures is not the way to do it.

Ion/Ioff - the ratio of how much current the transistor can source when it's supposed to be on, vs. the amount of current a transistor leaks when it's supposed to be off - is a very good benchmark to compare because leakage and transistor speed usually go hand in hand on a given process at a given company (so you can get great power numbers if you are willing to sacrifice speed bins), but the ratio usually has a "sweet spot" that can be used as a benchmark against other companies.

An absolutely excellent post pm!!!
There's a lot of stuff there, and I thank you...and now for the inevitable "but"... 🙂

1. On yields...obviously "poor" and "mature" are not percentages or costs... AMD has stated that their definition of "mature" for a new node is to have yields at least equivalent to the outgoing node. Companies don't disclose their yields, but analysts have calculated that AMD must have hit at least 85%+ on their current 90nm process (this is an average, because as you point out, it's quite reliant on the speed bins). The way they did this was easier than it would be for Intel...AMD sold out of their inventory. The calculation was 85%+ because that was the number required to actually deliver the number of chips they sold...(I'm not sure how many people know yields, but 85% is astoundingly high...70-80% is considered excellent)

Now here is the "wriggle room" for both companies...you can express yield as either a percentage of *dice/wafer, or the number of *dice/wafer...
Since Presler (for example) is 32% smaller than Smithfield, if you produced Smithfield at 75% yields you would only need Presler at 51% yields to be an equivalent number of dice/wafer. My guess is that the 65nm node is producing near the 35-50% yield range (slightly higher than what was achieved with Prescott at launch and close to a mature yield based on number of dice/wafer). Remember that this is a guess (based on volume offerings)...I'm sure that pm could tell us quite accurately, if he didn't mind getting both fired and sued. 🙂
Whatever it is though, I am quite confident that the percentage yield of the 65nm node is nowhere near the percentage yield of the 90nm node...yet.

2. Ion/Ioff - another excellent point sir...one of the things I've noted in the recent articles on AMD/IBMs new strained silicon process is that they now are using embedded SiGe with a dual stress liner on SOI. I don't know if you can say, but is this part of Intel's plans on 45nm?


*by dice I mean candidate dice

 

[Viditor]

Originally posted by: coldpower27

Originally posted by: Viditor
Well, Hector Ruiz stated those facts at a Conference call...which means if he's lying he can go to prison. The article you linked isn't even quoting anyone specific about the Intel yields, and certainly nobody in senior management (who could be held liable).
So, please forgive me if I remain dubious as to the articles claims...

Which conference call did Hector Ruiz make such statements?

The latest one...If I have time later, I'll try to find you a link.

 

[pm]

Originally posted by: Viditor
An absolutely excellent post pm!!!
There's a lot of stuff there, and I thank you...and now for the inevitable "but"... 🙂

1. On yields...obviously "poor" and "mature" are not percentages or costs... AMD has stated that their definition of "mature" for a new node is to have yields at least equivalent to the outgoing node. Companies don't disclose their yields, but analysts have calculated that AMD must have hit at least 85%+ on their current 90nm process (this is an average, because as you point out, it's quite reliant on the speed bins). The way they did this was easier than it would be for Intel...AMD sold out of their inventory. The calculation was 85%+ because that was the number required to actually deliver the number of chips they sold...(I'm not sure how many people know yields, but 85% is astoundingly high...70-80% is considered excellent)

Now here is the "wriggle room" for both companies...you can express yield as either a percentage of *dice/wafer, or the number of *dice/wafer...
Since Presler (for example) is 32% smaller than Smithfield, if you produced Smithfield at 75% yields you would only need Presler at 51% yields to be an equivalent number of dice/wafer. My guess is that the 65nm node is producing near the 35-50% yield range (slightly higher than what was achieved with Prescott at launch and close to a mature yield based on number of dice/wafer). Remember that this is a guess (based on volume offerings)...I'm sure that pm could tell us quite accurately, if he didn't mind getting both fired and sued. 🙂
Whatever it is though, I am quite confident that the percentage yield of the 65nm node is nowhere near the percentage yield of the 90nm node...yet.

2. Ion/Ioff - another excellent point sir...one of the things I've noted in the recent articles on AMD/IBMs new strained silicon process is that they now are using embedded SiGe with a dual stress liner on SOI. I don't know if you can say, but is this part of Intel's plans on 45nm?


*by dice I mean candidate dice

I always enjoy your posts, Viditor. That's an interesting way of calculating AMD's yield and, based on my years in the industry, I would say that it's probably fairly close to reality. As you mentioned, I do actually know down to a tenth of a percentage point the packaged yield (and the sort yield for that matter, too) for most of Intel's mainline products - I spent the better part of an afternoon a few days ago in a meeting going through them line by line - but, as you correctly pointed out, these numbers are considered core to Intel's business and that disclosing them would be a violation of SEC rules and Intel corporate policy. I often find myself in the position of knowing things, wanting to discuss them in detail, but having to sit back and say nothing. So I can't comment on your numbers, as much as I'd love to.

Intel has it's own approach to strained silicon that is similar (in concept anyway) to the method employed by AMD/IBM. That said, to be completely honest, I have a strong understanding of how the changes in 45nm are going to impact design, but I don't have as much knowledge as to what is physically happening on the process. I know the electrical characteristics of the transistors and the rules that we need to follow while drawing the mask, but not at all what the fab guys are physically doing to the transistors. I would imagine that this year's IEDM will have a lot of information on the subject though, so we only have to wait about 10 months. 🙂


Patrick Mahoney
Enterprise Microprocessor Division
Intel Corp.
Fort Collins, CO