I don't really understand the purpose of this chip.... unless just for research?
It's purely for development. They are trying to figure out how to better improve upon inter-core communications.
Amdahl's law tells you how much performance scaling is left on the table by the software programmers and app (the time spent processing serial code/operations) but Almasi & Gottlieb extended Amdahl's law to include the rate-limiting impact of inter-processor communications (also called IPC, and unfortunate duplication of the also commonly used acronym IPC = instructions per clock).
Almasi & Gottlieb tell you how much performance scaling is left on the table by the hardware design...the network fabric.
Here's a graphical example:
Ignore the yellow data points, look at the thick red line versus the green diamonds versus the aqua-blue circles.
The red line tells you how much performance scaling is theoretically possible with this application IF the hardware is designed in a way that eliminates IPC as a rate-limiting scaling component.
The Blue versus Green data points show you how well (or how poorly depending on your glass is half-full/half-empty mentality) the hardware enables scaling, showing you just how much scaling performance has been left on the table by these specific hardware implementations for this specific app.
Now scale the x-axis out to 48 cores...the gap between the red line and the data points is going to only get larger and larger...that is what Intel's 48-core chip is designed to figure out how to optimize.
FWIW the scaling performance can actually reach a maximum value and start to become worse as you add more cores/threads to the parallel computation.
Here's a generic example depicting what I mean:
