Intel demos 48 core chip

PottedMeat

Lifer
Apr 17, 2002
12,363
475
126
xcab9.jpg


that's a lot of SMA test connectors. bunch of voltage regulator modules up top with big ceramic resistors? maybe for monitoring current. wonder what that 4-pin male connector array is for - they look like old style power plugs.
 

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,787
136
Isn't this Larrabee with P5-derived cores?

P54C based cores

0.6um Pentium: First CPU based on P54C

Larrabee: Vector optimized P54C
Atom: General Purpose processing optimized P54C
Intel SCC(Single-chip Cloud Computer): P54C based many core project for developers. No changes on the core.

The clock frequency on the SCC is 1/2 of the mesh, and the top speed of the mesh is 2.0GHz meaning the cores run at 1GHz.
 
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RaiderJ

Diamond Member
Apr 29, 2001
7,582
1
76
They better build a board with more than 8 memory slots! Seems like not having any shared cached between cores is going to really add a lot of traffic to the memory subsystem.

I don't really understand the purpose of this chip.... unless just for research?
 

Idontcare

Elite Member
Oct 10, 1999
21,110
64
91
I don't really understand the purpose of this chip.... unless just for research?

It's purely for development. They are trying to figure out how to better improve upon inter-core communications.

Amdahl's law tells you how much performance scaling is left on the table by the software programmers and app (the time spent processing serial code/operations) but Almasi & Gottlieb extended Amdahl's law to include the rate-limiting impact of inter-processor communications (also called IPC, and unfortunate duplication of the also commonly used acronym IPC = instructions per clock).

Almasi & Gottlieb tell you how much performance scaling is left on the table by the hardware design...the network fabric.

Here's a graphical example:
Euler3DBenchmarkScaling.gif


Ignore the yellow data points, look at the thick red line versus the green diamonds versus the aqua-blue circles.

The red line tells you how much performance scaling is theoretically possible with this application IF the hardware is designed in a way that eliminates IPC as a rate-limiting scaling component.

The Blue versus Green data points show you how well (or how poorly depending on your glass is half-full/half-empty mentality) the hardware enables scaling, showing you just how much scaling performance has been left on the table by these specific hardware implementations for this specific app.

Now scale the x-axis out to 48 cores...the gap between the red line and the data points is going to only get larger and larger...that is what Intel's 48-core chip is designed to figure out how to optimize.

FWIW the scaling performance can actually reach a maximum value and start to become worse as you add more cores/threads to the parallel computation.

Here's a generic example depicting what I mean:
Impactofbroadcastprotocolonscaling.gif
 
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deimos3428

Senior member
Mar 6, 2009
697
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It's either for parallelized compute tasks or virtualized farms. Either way, the more cores you can pack in a rack unit, the better -- you want to save on colo power/heat/space whenever possible.
 

Idontcare

Elite Member
Oct 10, 1999
21,110
64
91
Is it related to this? "Knight's Corner" "MIC (Many Integrated Cores)"

http://www.intel.com/pressroom/archive/releases/2010/20100531comp.htm

From the link:

Products build upon Intel's history of many-core related research including Intel's "Larrabee" program and Single-chip Cloud Computer.

This thread's OP is in regards to the latter (single-chip cloud computer) but there appears to be a lot of commonalities between Larrabee and the SCC so it is not surprising that the two appear to be heading towards convergence at 22nm.

FWIW "MIC" is expressly Larrabee. The very silicon that is being sampled to partners is the same silicon that was sampled as Larrabee. Product codename redirection.

Aubrey_Isle_die.jpg

Die shot of Aubrey Isle silicon. Aubrey isle is the codename of the silicon chip included the 'Knights Ferry' Intel Many Integrated Core (MIC) architecture development platform.

^ This same dieshot and silicon was called Larrabee a year ago.
 

alyarb

Platinum Member
Jan 25, 2009
2,425
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That's funny. They call this the knights ferry "development card."

Intel_ISC_2010_Hamburg-KnightsFerry.jpg


But this is a 32 core, 45nm part. And knights ferry will be what, 64 cores on 22nm?
 
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Dec 30, 2004
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FWIW the scaling performance can actually reach a maximum value and start to become worse as you add more cores/threads to the parallel computation.

Here's a generic example depicting what I mean:
Impactofbroadcastprotocolonscaling.gif

it just occurred to me that's a perfect description of government :) the red line, to be exact ;)
 

tweakboy

Diamond Member
Jan 3, 2010
9,517
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www.hammiestudios.com
Relax guysl. This will not happen until 2014 to 2020 ///// no body gives a ratz, about a prototype,, Ive seen nice car prototype but does it ever come out no it doesnt....

take a deep breath man many years away we are from this tehcnology. thx
 

Idontcare

Elite Member
Oct 10, 1999
21,110
64
91
it just occurred to me that's a perfect description of government :) the red line, to be exact ;)

lol, yeah, red or green both depict the rise and inevitable fall of overly-bureaucratic governments. Since the dawn of time man has endeavored to find cleverer and cleverer ways to commit epic fail, it's in our genes I guess. Not that I know of an alternative, the alternatives tend to involve even more - and immediate - levels of carnage and misery.
 

taltamir

Lifer
Mar 21, 2004
13,576
6
76
It's either for parallelized compute tasks or virtualized farms. Either way, the more cores you can pack in a rack unit, the better -- you want to save on colo power/heat/space whenever possible.

unless those cores are super inefficienct pentium 1 class cores. Which is what we are looking at here.

this 48 core chip is inferior to nehalem. it is meant for software research (to create innovative new methods to scale to many cores)
 

Nemesis 1

Lifer
Dec 30, 2006
11,366
2
0
unless those cores are super inefficienct pentium 1 class cores. Which is what we are looking at here.

this 48 core chip is inferior to nehalem. it is meant for software research (to create innovative new methods to scale to many cores)


Were on earth did ya come up with that . Watch the video I linked . Its a co processor.

Tweak boy . Why is your info . greater than intels. Knights corner the end of 2011. Knights ferry is today . To develop software . So in late 2011 knights corner is ready to crush NV in the HPC market. and its much easier to program for . Why do ya think AMD announced their software programm. Intel just released there plan with actual product to develop for . But nice try at pure BS . Both you 2 guys.
 
Dec 30, 2004
12,553
2
76
lol, yeah, red or green both depict the rise and inevitable fall of overly-bureaucratic governments. Since the dawn of time man has endeavored to find cleverer and cleverer ways to commit epic fail, it's in our genes I guess. Not that I know of an alternative, the alternatives tend to involve even more - and immediate - levels of carnage and misery.

the only alternative is an external standard that people are held accountable to-- God.

If we understood our identity in God, we would not desire to sin. It would be beneath us. And so trying to get away with wasting time and doing nothing (something that government is amazing at encouraging and epically fails at punishing) would not be desirable to us.
The "in our genes" that you speak of is sin./preachpreachpreach
 
Dec 30, 2004
12,553
2
76
Relax guysl. This will not happen until 2014 to 2020 ///// no body gives a ratz, about a prototype,, Ive seen nice car prototype but does it ever come out no it doesnt....

take a deep breath man many years away we are from this tehcnology. thx

you know you usually have obviously trollish posts (don't worry I've come to develop a fond affection for them) but I completely agree with you on this one.
 

mutz

Senior member
Jun 5, 2009
343
0
0
It's purely for development. They are trying to figure out how to better improve upon inter-core communications.

Amdahl's law tells you how much performance scaling is left on the table by the software programmers and app (the time spent processing serial code/operations) but Almasi & Gottlieb extended Amdahl's law to include the rate-limiting impact of inter-processor communications (also called IPC, and unfortunate duplication of the also commonly used acronym IPC = instructions per clock).

Almasi & Gottlieb tell you how much performance scaling is left on the table by the hardware design...the network fabric.

Here's a graphical example:
<zip>

Ignore the yellow data points, look at the thick red line versus the green diamonds versus the aqua-blue circles.

The red line tells you how much performance scaling is theoretically possible with this application IF the hardware is designed in a way that eliminates IPC as a rate-limiting scaling component.

The Blue versus Green data points show you how well (or how poorly depending on your glass is half-full/half-empty mentality) the hardware enables scaling, showing you just how much scaling performance has been left on the table by these specific hardware implementations for this specific app.

Now scale the x-axis out to 48 cores...the gap between the red line and the data points is going to only get larger and larger...that is what Intel's 48-core chip is designed to figure out how to optimize.

FWIW the scaling performance can actually reach a maximum value and start to become worse as you add more cores/threads to the parallel computation.

Here's a generic example depicting what I mean:
,<zzzip>

this is a brilliant post!
 

Idontcare

Elite Member
Oct 10, 1999
21,110
64
91
we have our random lucid moments here in the forums but they usually don't get noticed, thx for noticing and I'm glad you enjoyed it
toast2.gif