Intel delays 14 nm KabyLake to 2016H2/2017Q1, 10 nm Cannonlake to 2017H2/2018Q1

[videogames101]

There are indications that design of at least one 10nm SoC is underway, using TSMC's 10nmFF process, the ARM ARTEMIS core, ARM 10nm physical IP and Synopsys tools; my guess is that MediaTek may be developing a SoC; the 10nm process is available now, and HVM will begin in 2016 Q4.

Some sceptics say that this is not a true 10nm process, citing some limited information on transistor sizes; however, this ignores the sizing of ARM's Physical IP transistors, which, as I understand it, include three different transistor designs, with different sizes;
see for example:
http://www.arm.com/assets/images/PIPD_Logic_IP_Intro_large.jpg

Given the choice of transistor sizes available, it is not a simple matter to dismiss the use of the 10nm label; there is obviously a wide variation in transistor density. Ultimately, it is the real-world performance of the SoC that will count.

ARM's Physical IP seems to be a part of the 10nm process itself, since it involves actual transistor design; it seems that the Physical IP exists at a lower level than the RTL that constitutes the design of a core, such as A72.

I would be very interested in an Anandtech article explaining the role of ARM's Physical IP.

Physical IP consists of some or all of the following: Standard Cell Libraries, Memory Compilers, IO Drivers. All of these are transistor level circuit designs in the form of repeatable blocks you can place down to create a digital circuit.

These are used for implementing RTL, and ARM is happy to sell you their CPU RTL along with Physical IP to implement it - for a higher price. Of course there are many other Physical IP vendors, not the least of which are the various foundries themselves.

 

[Fjodor2001]

So is the conclusion that SRAM cell size alone cannot be used to determine actual transistor density of various process techs?

And is there some other process tech property that can be use for comparison instead that is valid regardless of which of these Physical IP transistor types is chosen:

Or do we have to compare the size of one specific type of transistor to make a fair comparison? E.g. what size the "High Density" transistor will have on Intel/TSMC/Samsung/GF 10 nm.

 

[ShintaiDK]

SRAM is the best compare of density and very precise. However same standard libraries must be used. As well as the same SRAM cell blocks. Aka no 6T vs 8T for example or HP vs HD.

Density however doesn't say anything about electrical properties. But it got an large impact on it in terms of library used

 

[videogames101]

So is the conclusion that SRAM cell size alone cannot be used to determine actual transistor density of various process techs?

And is there some other process tech property that can be use for comparison instead that is valid regardless of which of these Physical IP transistor types is chosen:

Or do we have to compare the size of one specific type of transistor to make a fair comparison? E.g. what size the "High Density" transistor will have on Intel/TSMC/Samsung/GF 10 nm.

You can't just compare a single figure to determine density. It's much more complicated. For example, using something like a 7-Track library can limit your horizontal routing tracks because your power grid is more dense (Look at the distance between the top and bottom M1 VDD and VSS rails on those cell layouts, they're in blue). For some wire-dominated designs that will actually increase chip size compared to a 9T or 10T library. If you you really want to find out differences in density, look at overall chip size. (The A9 example with TSMC and Samsung is perfect.)

 

[Fjodor2001]

If you you really want to find out differences in density, look at overall chip size. (The A9 example with TSMC and Samsung is perfect.)

Yes, but the problem is that it's rare to have the same design produced on different process techs. A9 being on both Samsung 14 nm and TSMC 16 nm is an exception. So how do we then compare e.g. TSMC vs Intel 10 nm process tech with regards to density? I don't think there'll be an identical chip design produced on both of them.

 

[videogames101]

Yes, but the problem is that it's rare to have the same design produced on different process techs. A9 being on both Samsung 14 nm and TSMC 16 nm is an exception. So how do we then compare e.g. TSMC vs Intel 10 nm process tech with regards to density? I don't think there'll be an identical chip design produced on both of them.

SRAM cell size and metal density are good proxies. :thumbsup:

(but not that good)

 

[Thala]

SRAM cell size and metal density are good proxies.

There is no single SRAM cell size even if you restrict yourself to 7 tracks. Actual size depends on required performance and performance depends on word width/depth of selected SRAM cells from the library, which again impacts area.
Of course foundries are bragging about their high density SRAM cells, but without any performance numbers this has not much meaning.