Discussion Intel current and future Lakes & Rapids thread

[Timmah!]

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Lenovo ThinkStation PX Dual SPR and the Xeon W Duo P7 and P5 Launched

The Lenovo ThinkStation PX workstation houses dual 4th Gen Intel Xeon processors while the P7 uses a Xeon W-3400 and the P5 has a Xeon W-2400

www.servethehome.com

Sapphire Rapids based 3 workstations announced by Lenovo. Very tempted to get a quote for the PX, but I think I’ll wait for Granite Rapids.

Yeah, those will cost about the same as said Aston Martin.

 

[ashFTW]

Yeah, those will cost about the same as said Aston Martin.

I’m thinking about $20k for 120 cores, 1TB memory, and min GPU based on my previous experience with Lenovo reps for my University. Though prices are sky high for everything these days, so who knows..

 

[Edrick]

What a load of crap.
in a compute dense rack you can go 4 sockets an RU , people most certainly care about 88kw of CPU vs 52kw*. That is significate power and cooling works and that's just CPU budget .
Even if you go for something more sane like 2 P an RU 44kw vs 26kw is still stupid bad.

i buy lots of servers for NFV purpose i can about maximum number of cores (HT off) with maximum clock rate with scalar / narrow SIMD widths , biggest SIMD user will be TLS decrypt/ encrypt .

Most server workload will never care about AVX-512 or AMX. So unless your telling orgs not to buy intel unless they need AMX really because Zen4 does AVX-512 just fine.

* 48ru with 4ru of switching 44ru of scale out compute , 6 x2.5inch drives a server , 1/2 width 2P server.

Read what I wrote again.

I said people who buy these types of Xeons (for AVX512 and AMX) are less concerned with total power output from these racks. I never said all server buyers don't care about power. Of course there are plenty of instances where efficiency is preferred (that's why you see smaller, lower power cores breaking into the server market). And for NFV that is the case.

 

[semiman]

Exactly. Server CPUs are not designed to have mobile level power requirements due to a lot of other die area needed for extensions like AVX512 and AMX. And to be honest, the people who buy these types of Xeons are not concerned about 300W vs. 500W.

It matters a lot. Performance per power and performance per density(Server rack density), performance per platform all matters.

 

[nicalandia]

I’m thinking about $20k for 120 cores, 1TB memory, and min GPU based on my previous experience with Lenovo reps for my University. Though prices are sky high for everything these days, so who knows..

Its $34K just on the CPUs alone.

 

[nicalandia]

Xeon W9-2465X AIDA64 Results DDR5 6000



Due to Mesh Interconnect the latencies are High on these CPUs

 

[msj10]

Leaked RWC slide from Adoredtv, He says it's from 2 years ago.

 

[Timmah!]

I’m thinking about $20k for 120 cores, 1TB memory, and min GPU based on my previous experience with Lenovo reps for my University. Though prices are sky high for everything these days, so who knows..

I have to wonder how loud those sandwiched Quadros on top of each other will be.
Otherwise its a nice build. I would be OK even with that 24 core version :-D... but only Ampere cards? Whyyyyyy.... no bueno.

 

[Hulk]

Intel process schedule. I don't understand the progression?

Intel 7 ~ 10nm
Intel 4 ~7nm
Intel 20A ~ 2nm
Intel 18A ~ 1.8nm

Am I missing something or is there a huge jump between Intel 4 and Intel 20A?
And why such a tiny difference between 20A and 18A?

 

[jpiniero]

Node names have been meaningless from a technical perspective for some time now.

 

[Hitman928]

Node names have been meaningless from a technical perspective for some time now.

This is true, but @Hulk is still correct. Intel is jumping from ~7nm to 20A which is a GAAFET node. TSMC has 10, 7, 5, and 3 (plus tweaked versions for each) before moving to GAAFET at 2/20A. Samsung also had a 5 node before moving to GAAFET at 3 and is scheduled to move to 2/20A in 2025. Intel is trying to catch up (and even leap over) the others and is jumping forward a bit comparatively.

Also, from what I've seen discussed/rumored online, Intel's 20A and 18A are basically the same process. It's just that 20A doesn't have all of the features and cell libraries available yet.

 

[nicalandia]

More AIDA64 Numbers.

 

[jpiniero]

This is true, but @Hulk is still correct.

Let me rephrase - it's literally marketing. Intel could call it's nodes whatever it likes. I don't think Intel's made any actual claims yet as to density or quality.

 

[Hulk]

Let me rephrase - it's literally marketing. Intel could call it's nodes whatever it likes. I don't think Intel's made any actual claims yet as to density or quality.

True I just don't see the marketing advantage for Intel. We are going to expect 20A to be better than TMSC 3nm. And where are they going after 18A? It just seems like they could have planned these shrinks better in terms of naming.

 

[Hitman928]

Let me rephrase - it's literally marketing. Intel could call it's nodes whatever it likes. I don't think Intel's made any actual claims yet as to density or quality.

This is true. But @Hulk is still correct when looking at things technologically. Intel is making a bigger jump from FinFET to GAAFET than the other two foundries. They are also introducing more new tech (e.g backside power) in fewer steps than the others.

 

[jpiniero]

Intel is making a bigger jump from FinFET to GAAFET than the other two foundries.

Again, Intel hasn't made any claims about 20A or 18A (that I'm aware of ). GAAFET is cool but it's too early to draw any conclusions versus TSMC and Samsung.

As I've been saying I'm expecting the nodes to be in a pre-alpha type state when they introduce products using it. That is, if things don't get delayed. TSMC and Samsung aren't going to do that.

 

[coercitiv]

True I just don't see the marketing advantage for Intel. We are going to expect 20A to be better than TMSC 3nm. And where are they going after 18A? It just seems like they could have planned these shrinks better in terms of naming.

Let me help with a blast from the past:

2020, Intel 10nm SuperFin (10SF): Current generation technology in use with Tiger Lake and Intel’s Xe-LP discrete graphics solutions (SG1, DG1). The name stays the same.

2021 H2, Intel 7: Previously known as 10nm Enhanced Super Fin or 10ESF. Alder Lake and Sapphire Rapids will now be known as Intel 7nm products, showcasing a 10-15% performance per watt gain over 10SF due to transistor optimizations. Alder Lake is currently in volume production. Intel’s Xe-HP will now be known as an Intel 7 product.

2022 H2, Intel 4: Previously known as Intel 7nm. Intel earlier this year stated that its Meteor Lake processor will use a compute tile based on this process node technology, and the silicon is now back in the lab being tested. Intel expects a 20% performance per watt gain over the previous generation, and the technology uses more EUV, mostly in the BEOL. Intel’s next Xeon Scalable product, Granite Rapids, will also use a compute tile based on Intel 4.

2023 H2, Intel 3: Previously known as Intel 7+. Increased use of EUV and new high density libraries. This is where Intel’s strategy becomes more modular – Intel 3 will share some features of Intel 4, but enough will be new enough to describe this a new full node, in particular new high performance libraries. Nonetheless, a fast follow on is expected. Another step up in EUV use, Intel expects a manufacturing ramp in the second half of 2023 with an 18% performance per watt gain over Intel 4.

2024, Intel 20A: Previously known as Intel 5nm. Moving to double digit naming, with the A standing for Ångström, or 10A is equal to 1nm. Few details, but this is where Intel will move from FinFETs to its version of Gate-All-Around (GAA) transistors called RibbonFETs. Also Intel will debut a new PowerVia technology, described below.

2025, Intel 18A: Not listed on the diagram above, but Intel is expecting to have an 18A process in 2025. 18A will be using ASML’s latest EUV machines, known as High-NA machines, which are capable of more accurate photolithography. Intel has stated to us that it is ASML’s lead partner when it comes to High-NA, and is set to receive the first production model of a High-NA machine. ASML recently announced High-NA was being delayed- when asked if this was an issue, Intel said no, as the timelines for High-NA and 18A are where Intel expects to intersect and have unquestioned leadership.

Funny how the older names eliminate the "too big a jump" issue Like @jpiniero said, it's all marketing.

 

[Geddagod]

Again, Intel hasn't made any claims about 20A or 18A (that I'm aware of ). GAAFET is cool but it's too early to draw any conclusions versus TSMC and Samsung.

As I've been saying I'm expecting the nodes to be in a pre-alpha type state when they introduce products using it. That is, if things don't get delayed. TSMC and Samsung aren't going to do that.

From purely a perf/watt perspective, I'm guessing Intel 20A is going to better than TSMC 3nm. Assuming Intel 7 is equal to TSMC 7nm in perf/watt, Intel should be ahead. By a good margin too, Intel 7 to 4 is an entire node jumps worth of performance, 3 to 4, while might not have the same leap in density, is the same node jump in perf/watt, and Intel 3 to Intel 20A is also a node jumps worth of perf/watt. So that's 3 nodes worth of perf/watt gains between Intel 7 and Intel 20A, while TSMC 7 to TSMC 3nm is just 2 (TSMC 7>TSMC5>TSMC3).
There's even an argument that Intel 10ESF could be equal to TSMC 7nm in perf/watt, and Intel 7 is 10-15% better than Intel 10ESF, which again, is pretty much a full node jump.
Intel struggles in low perf at low voltages though. Whether this is an issue with their nodes, or their architecture designs, remains to be seen.

 

[Geddagod]

Leaked RWC slide from Adoredtv, He says it's from 2 years ago.

View attachment 77923

20% core performance. Notice how it says due to power/perf improvement, and not from IPC or clocks. Seems to me this continues to indicate RWC focuses on efficiency.
GNR HBM got cancelled a while back I heard.
High bandwidth/core... a reference to the increased L2 per core for RWC vs GLC? Maybe? Don't think so because GLC server had 2MB of L2, as does RWC Client, but I suppose it's possible RWC L2 increases in server as well? Could be referring to the potential increased amount of L1i per core as well, RWC supposedly bumps that up in comparison to GLC. Lastly, this could also be referring to an increase in L3 cache. EMR is rumored to increase L3 cache quite substantially per core, so I would be surprised if RWC didn't carry that over to GNR, or atleast higher amounts per core than SPR.

 

[ashFTW]

Its $34K just on the CPUs alone.

View attachment 77918

There is usually a big difference with university pricing. And I’m sure intel is motivated to make big discounts to its big OEMs. Maybe it will be a few thousands more, but not more than 25k. Performance wise it’s approx double of my current workstation that I got for 10k. I usually don’t upgrade till there is a 3-4x multithread improvement, so I’m likely to skip this generation.

 

[jpiniero]

There is usually a big difference with university pricing. And I’m sure intel is motivated to make big discounts to its big OEMs. Maybe it will be a few thousands more, but not more than 25k. Performance wise it’s approx double of my current workstation that I got for 10k. I usually don’t upgrade till there is a 3-4x multithread improvement, so I’m likely to skip this generation.

Unless you are expecting to use AMX, why bother and just roll with Genoa?

 

[nicalandia]

There is usually a big difference with university pricing. And I’m sure intel is motivated to make big discounts to its big OEMs. Maybe it will be a few thousands more, but not more than 25k. Performance wise it’s approx double of my current workstation that I got for 10k. I usually don’t upgrade till there is a 3-4x multithread improvement, so I’m likely to skip this generation.

Sure, dream on...

 

[Edrick]

Due to Mesh Interconnect the latencies are High on these CPUs

Unfortunately, its been that was since Skylake SP. I had to overclock the mesh by 25% on my Cascade Lake-X CPU just to get close to the latencies of their desktop CPUs. But it appears to be even worse for SPR.

 

[Edrick]

More AIDA64 Numbers.

View attachment 77927

I think this is rather misleading. Those numbers look like quad channel for that speed RAM. Remember that not all motherboards support 8 channel memory even though they support those CPUs. The ASRock board used here does NOT support 8 channel.

 

[Hulk]

From purely a perf/watt perspective, I'm guessing Intel 20A is going to better than TSMC 3nm. Assuming Intel 7 is equal to TSMC 7nm in perf/watt, Intel should be ahead. By a good margin too, Intel 7 to 4 is an entire node jumps worth of performance, 3 to 4, while might not have the same leap in density, is the same node jump in perf/watt, and Intel 3 to Intel 20A is also a node jumps worth of perf/watt. So that's 3 nodes worth of perf/watt gains between Intel 7 and Intel 20A, while TSMC 7 to TSMC 3nm is just 2 (TSMC 7>TSMC5>TSMC3).
There's even an argument that Intel 10ESF could be equal to TSMC 7nm in perf/watt, and Intel 7 is 10-15% better than Intel 10ESF, which again, is pretty much a full node jump.
Intel struggles in low perf at low voltages though. Whether this is an issue with their nodes, or their architecture designs, remains to be seen.

I don't think it's unrealistic to say that Intel 7 (current) aka 10nm+++++ ~ TMSC 7.

But TMSC 5 is a pretty large improvement over TMSC 7, sure power has gone up but clocks have increased dramatically.

I'll be impressed if Intel 4 is better than TMSC 5. Actually let me rephrase that. I'll be impressed if they can do it in the next year. I'm sure they'll get there but if it takes 4 years who cares?