Discussion Intel current and future Lakes & Rapids thread

[Det0x]

I just noticed that that 142W idle power is just for high performance power management in Windows, normal balanced setting causes "just" 50W power draw, which is comparable with Threadripper.

But what happens to performance in bursty workloads when you allow cores/part of the CPU to go to sleep ?

In the two charts above, we are showing performance across the lightly and moderately threaded applications we will be looking at throughout this article. More highly threaded tasks like CPU rendering are largely unaffected, so we left them out of the chart. As you can see, for AMD’s Threadripper PRO CPUs, switching between the default “Balanced” and “High Performance” power profiles doesn’t make much difference for performance. A few percent here or there, but nothing significant.

The previous generation Intel Xeon W-3300 Series processors, however, can see anywhere from just a few percent to almost a 50% increase in performance by changing the Windows power profile. That is a big difference, but it turns out to be even more significant with the new Xeons. For the high core count Intel Xeon W-3495X 56 Core in particular, we are seeing anywhere from 20% to more than 2x higher performance when using the “High Performance” power profile.

Changing the power profile is not just free performance, and has a downside in that it tends to increase the power draw of the CPU while idle and when under light loads. We have recently been running HWiNFO alongside our benchmarks, and one of the things it can log is the total CPU package power. This is based on sensor data, so maybe slightly off from the actual power draw, but it should be more than accurate enough to give us a good picture of how the Windows power profile impacts the power draw. This gets very complex when broken down by workload, but it is easy enough for us to calculate the idle, maximum, and average power draw across an entire benchmark run.

Intel Xeon W-3400 Content Creation Preview

Intel has announced their latest Xeon processor families, including the W-2400 and W-3400 lines. While there is still several months to go before the sales embargo, we are able to give a preview of how these processors perform in various content creation applications.

www.pugetsystems.com

 

[nicalandia]

.....

I just noticed that that 142W idle power is just for high performance power management in Windows, normal balanced setting causes "just" 50W power draw, which is comparable with Threadripper.

PugetSystem said that they decided to use high performance profile because balanced profile its performed worst. Even losing to Zen2 based 3995WX. I Will post the numbers later today

 

[mikk]

Intel simultaneously claiming node leadership by 2024 while also shipping all their products on TSMC nodes is hilarious.

2024 too early. Gelsinger claimed leadership by 2025 with 20A+18A in the last Capital Allocation Update.

 

[coercitiv]

PugetSystem said that they decided to use high performance profile because balanced profile its performed worst.

Sounds like the product isn't really ready. Maybe they'll fix the power management issues in a timely manner though, it could just be firmware related.

I hope some of the folks on the forum who were waiting for HEDT will bite the bullet and build some systems. Given the initial reports about power usage I'd like to hear more from people who take the time to tinker with UEFI settings and updates.

 

[coercitiv]

I'd say the opposite. MTL is much more ambitious. SPR is basically a monolithic chip cut into quarters, but MTL has new and unique interfaces for individual tiles. Also, EMIB vs Foveros.

I think you're glossing over the challenges of makign SPR tiles behave like a monolithic chip. They had to double down on EMIB connections as opposed to a more conservative approach with a hub tile. Ian Cutress also mentioned the design must have faced significant engineering challenges from a thermodynamic PoV as well, due to thermal expansion in a dynamic, high power environment.

Then again, I probably underestimate the challenges of building MTL on Foveros, I ran with the idea that it's their second gen interface and this time around they don't have another tile on the vertical plane.

 

[nicalandia]

I hope some of the folks on the forum who were waiting for HEDT will bite the bullet and build some systems. Given the initial reports about power usage I'd like to hear more from people who take the time to tinker with UEFI settings and updates.

It's not encouraging when a Stock Water Cooled Zen2 based 3995WX is as fast as a Stock Water Cooled Xeon W9 3495X, a lightly tune 3995WX that consumes 430 Watts is faster than a unrestricted 500 watt Xeon W9 3495X.

Also two 3995WX(5995WX as well) can be run on a Server Motherboard and two of those can score higher than 100,000 points in Cinebench R23 at stock settings

 

[Timmah!]

So what is happening? Intel is moving Arrow Lake to TSMC 3nm and there will be Raptor Lake Refresh first, perhaps as result of the possible delay caused by that?

 

[Joe NYC]

So what is happening? Intel is moving Arrow Lake to TSMC 3nm and there will be Raptor Lake Refresh first, perhaps as result of the possible delay caused by that?

Raptor Lake Refresh seems to me like a contingency plan, in case of the subsequent CPU designs are delayed (rather than it being the cause of delays).

 

[DrMrLordX]

I already wrote this:

That's one core. Granted CBR23 isn't notorious for taxing interconnect, but it would still be better to utilize all 8 cores on an Alder Lake and then make a comparison.

It can't be 10nm, my 12700K does ~17.5K points in CB23 with 8+0 config and PL1=PL2=125W. Cores oscillate between 4.2 and 4.3 GHz, VCore is around 1,15V (as opposed to 1V for 4.2Ghz that I saw being discussed earlier for SPR). If I force the cores to run at base speed, then the CPU scores 14K+ while using 70W. So a hypothetical 32 core ADL chip using older gen Intel 7 lithography, could score close to 70K in CB23 and use exactly 500W. A 56 core ADL could still use 500W and score 90-100K in CB23.

So it's either a problem with the core, or a problem with moving data around.

And that's the sort of datapoint we're looking for. Thanks!

 

[Kocicak]

That's one core. Granted CBR23 isn't notorious for taxing interconnect, but it would still be better to utilize all 8 cores on an Alder Lake and then make a comparison.

I find the scores to be almost perfectly additive. If you want performance of 8 cores, just multiply it with 8. Frequency scaling also works very well, unless you hit some thermal or power limits.

 

[Kocicak]

Where are all the reviews. Intel did not sample these CPUs to reviewers? Why?

 

[nicalandia]

Where are all the reviews. Intel did not sample these CPUs to reviewers? Why?

They are busy selling those big 4 tile CPUs for higher profit as Xeon Platinum. There are very few of those as it is. They just built very few of those(Xeon W9) and did a paper launch. Availability will be on March

 

[Timmah!]

Raptor Lake Refresh seems to me like a contingency plan, in case of the subsequent CPU designs are delayed (rather than it being the cause of delays).

What would it look like? Could it be the fabled 8 + 32 chip? I dont see what else can Intel do except another cache increase.
Anyway, this could force AMDs hand regarding more cores on Ryzen in Zen5.

 

[Kocicak]

They are busy selling those big 4 tile CPUs for higher profit as Xeon Platinum. There are very few of those as it is. They just built very few of those(Xeon W9) and did a paper launch. Availability will be on March

They do not even have 3-5 systems fo send out? Weird.

 

[nicalandia]

They do not even have 3-5 systems fo send out? Weird.

They simply don't have enough samples and the stock performance is underwhelming(Rome based Threadripper class) so they don't have any incentive to ship many review samples.

 

[Joe NYC]

What would it look like? Could it be the fabled 8 + 32 chip? I dont see what else can Intel do except another cache increase.
Anyway, this could force AMDs hand regarding more cores on Ryzen in Zen5.

My theory is that Intel will just create a new die with larger L3, and make it available only as a couple of high end SKUs - in order to try to neutralize Zen 4 V-Cache

That would be the cheapest from the POV of design resources.

IMO, it would be foolish for Intel to devote a large design team for a major iteration of Raptor Lake, while the other major design projects desperately need resources.

Intel is switching to chiplet based approach across the entire product line, which is more strategic for future of Intel than the last tweak of Raptor Lake.

 

[A///]

Hair brained idea as Zen 5 is due in Q2 of 2024. With most of the pandemic well behind us we should be getting back on schedule. What is this of Arrow Lake being delayed until 2025? Is this due to Apple? What's coming in next fall if this fall is a refreshed Raptor?

 

[Exist50]

I think you're glossing over the challenges of makign SPR tiles behave like a monolithic chip. They had to double down on EMIB connections as opposed to a more conservative approach with a hub tile. Ian Cutress also mentioned the design must have faced significant engineering challenges from a thermodynamic PoV as well, due to thermal expansion in a dynamic, high power environment.

Then again, I probably underestimate the challenges of building MTL on Foveros, I ran with the idea that it's their second gen interface and this time around they don't have another tile on the vertical plane.

Architecturally, at least, the SPR approach is very simple. Take a monolithic die, draw some lines, and flop anything than crosses them over EMIB. It might not be ideal from a PnP or cost perspective, but it should be simple. A hub approach actually requires some rework of the interfaces, but is most likely a better long-term solution. Ultimately, I imagine Intel will move in that direction with UCIe.

And have there been any reviews of the monolithic SPR die? Because that should give us far more insight into the EMIB overhead. I suspect it won't look all that much better.

 

[Exist50]

Hair brained idea as Zen 5 is due in Q2 of 2024. With most of the pandemic well behind us we should be getting back on schedule. What is this of Arrow Lake being delayed until 2025? Is this due to Apple? What's coming in next fall if this fall is a refreshed Raptor?

I imagine the timeline is something like RPL-R (specs unknown) sometime around summer-ish, Zen 5 around the same next year, and Arrow Lake maybe just in time for the holidays. There's likely going to be a few months where Raptor Lake has to hold off Zen 5, but I imagine Intel will push to minimize it.

 

[nicalandia]

And have there been any reviews of the monolithic SPR die? Because that should give us far more insight into the EMIB overhead. I suspect it won't look all that much better.

No benchmarks yet for the Monolithic Die CPUs.

 

[Exist50]

No benchmarks yet for the Monolithic Die CPUs.

Hm, and I haven't seen anyone experiment with sub-NUMA clustering yet either. Reviewers getting a bit lazy.

 

[nicalandia]

Hm, and I haven't seen anyone experiment with sub-NUMA clustering yet either. Reviewers getting a bit lazy.

PugetSystem System hardly go byond Power Plan selection. Dont expect any OC or tweaking from them. Serve the home does that. But they didnt get any review samples. We just have to wait

 

[coercitiv]

Monolithic results will be interesting indeed.

 

[Exist50]

PugetSystem System hardly go byond Power Plan selection. Dont expect any OC or tweaking from them. Serve the home does that. But they didnt get any review samples. We just have to wait

Does anyone even know what the default SNC mode is for SPR-W? Doubt it matters for, say, Cinebench, but I'd think PugetBench would be a little more interesting.

 

[igor_kavinski]

What's coming in next fall if this fall is a refreshed Raptor?

Refresh of refreshed Raptor, possibly on Intel 4.