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Discussion Intel current and future Lakes & Rapids thread

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nicalandia said:
Hey look, LN2 World Record...

View attachment 76997


128,000 Points at 1600 Watts...

Thing is... The 7995WX will beat that at stock....
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And the 7763 Milan (that I have 2 of) can do 113,631on AIR COOLING, and stock. Kind of puts that LN2 result to shame.
bit-tech.net

AMD Epyc 7763 setup busts Cinebench R23 world record | bit-tech.net

System used twin CPUs for 128C/256T, and packed 512GB of RAM.
bit-tech.net bit-tech.net

1677093572468.png

And this is Geoa
"The performance was benchmarked within the Cinebench R23 benchmark. The Cinebench R23 CPU benchmark can only handle up to 256 threads and considering that there are two 96-core and 192-thread chips running on the platform for a total of 192 cores and 384 threads, only 66% of the CPU threads were active. Despite that, the AMD EPYC Genoa ES CPUs delivered over 110K points. This is a stock score and we can see that the chip boosted around 3.76 GHz though only when running a single-thread. In the single-core score, the chip scored 1302 points. '
 
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nicalandia said:
Going by PSU, but if you check the 4.2 Ghz all core OC it consumes 1,000 Watts
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I agree, judging by the 1100w in GB5 @ 4.2ghz 1.0v in previous intel PR video also suggest to me that these LN2 benches would be way higher in power usage.. I was just wondering if you had some information i was missing 🙂

I'm also interested in these new SR interconnects and their memory performance characteristics, especially the latency numbers. GB3 seem to indicate pretty bad memory performance.
1677093270216.png

On Zen4 i can get alittle over 14k multicore score and with RaptorLake above 16k is possible
 
coercitiv said:
So, Intel's second attempt at disaggregating their chips has again resulted in poor energy efficiency.

Let's hope third time is indeed the charm with MTL, otherwise nasty things will happen. Under no circumstance whatsoever can Intel afford to have poor efficiency with a mainstream mobile product. Luckily MTL has a relatively safer approach to tiles than SPR or Lakefiled, so fingers crossed until... unspecified time during H2 2023.
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How do we know it's because of chiplets again?
 
Det0x said:
I agree, judging by the 1100w in GB5 @ 4.2ghz 1.0v in previous intel PR video also suggest to me that these LN2 benches would be way higher in power usage.. I was just wondering if you had some information i was missing 🙂

I'm also interested in these new SR interconnects and their memory performance characteristics, especially the latency numbers. GB3 seem to indicate pretty bad memory performance.
View attachment 77001

On Zen4 i can get alittle over 14k multicore score and with RaptorLake above 16k is possible
Click to expand...

Extreme cold tends to have a significant effect on power usage at the same frequency, i.e. your processor power dissipation decreases with lower temperatures.
 
Geddagod said:
How do we know it's because of chiplets again?
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We don't, just like we didn't know anything with Lakefield either. It just so happens that their tile based attempts are using too much power. The one thing Lakefiled and SPR have in comon though is the ambition of the project: Intel has decided they can skip a mediocre chiplet implementation and aim directly at something more advanced, like 3D stacking with Lakefield or monolithic-like behavior with SPR (with multiple data paths between them, the tiles theoretically behave like one big chip).

By contrast MTL is more conservative, closer to what one would expect for Intel's first try. Whether that matters or not we'll see later this year.
 
coercitiv said:
We don't, just like we didn't know anything with Lakefield either. It just so happens that their tile based attempts are using too much power. The one thing Lakefiled and SPR have in comon though is the ambition of the project: Intel has decided they can skip a mediocre chiplet implementation and aim directly at something more advanced, like 3D stacking with Lakefield or monolithic-like behavior with SPR (with multiple data paths between them, the tiles theoretically behave like one big chip).

By contrast MTL is more conservative, closer to what one would expect for Intel's first try. Whether that matters or not we'll see later this year.
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I'd say the opposite. MTL is much more ambitious. SPR is basically a monolithic chip cut into quarters, but MTL has new and unique interfaces for individual tiles. Also, EMIB vs Foveros.
 
Combined with the rumors of Intel moving 3nm wafer orders to end of 2024
We are well into the ramp of 13th Gen Intel® Core™ and 4th Gen Intel® Xeon® Scalable processors, and we look forward to the launch of Meteor Lake and Emerald Rapids in 2023 and Granite Rapids and Sierra Forest in 2024.”
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No mention of ARL in 2024. And it's not like they ignored client products- MTL was still mentioned for 2023. I still think ARL will launch in 2024 (I don't really believe the 3nm delays by Intel unless it's actually a design problem and they can't launch in time...) but this will just add fuel to the fire that ARL is now a 2025 product.
 
nicalandia said:
I told you so.

It's not about the Core uArch. Golden Cove and Raptor Cove are very good and efficient cores... But this time Intel just choked them with small L3$, and slow Mesh Interconnect.
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I think they messed up much more than that. C23 doesn't need core-to-core communication, so it should work if cores are well-fed by memories. But its performance is practically on par with 13900K(with uses dual channels + 16 E cores).
 
Hulk said:
Yes, I totally forgot about

Cannon Lake 10nm 3.2GHz
Ice Lake 10+ 4.1GHz
Tiger Lake 10++ 5GHz
Alder Lake 10+++ 5.5GHz
Raptor Lake 10++++ 6GHz
Raptor Lake Refresh 10+++++

Now we're back in the "+" business again!

What frequency improvements could RLR bring?
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Raptor Lake Refresh may be as little as a new die with more L3, and releasing it for a couple of high end SKUs.

Just to try to neutralize Zen 4 V-Cache, and not spend a lot of design resources to accomplish this.
 
Exist50 said:
You are. Intel's communications have been confusing, but ARL is using some combination of N3 and 20A, with the latest rumor being N3 for desktop, and 20A for mobile.
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The interpretations of Intel slides I have seen suggested GPU is TSMC N3 and CPU tile is Intel 20A.

If Intel switches that for desktop and uses N3 for both, what does it say about the state of readiness of 20A and 5 nodes in 4 years?

It would have to mean that the process technology + manufacturing side is the bottleneck, not the design side (to timely release of Arrow Lake)
 
Ok I think we got a lot of good info from the latest Intel announcement today, more than people are talking about imo....
First of all, Intel claims ARL and TSMC 3nm are on schedule and not delayed
Intel 18A customer announcement later this year
And the rest of the stuff about nothing being delayed blah blah blah
But what's important is that Pat claimed Intel 20A product ramp is late 2024. This all but confirms, imo, that the schedule is for ARL on Intel 20A to launch early 2025. At best late 2024, but I doubt that.
The distinction here is product ramp. When Intel talks about node ramps, it could mean anything. For example, Intel 4 has been ready to ramp according to Intel since the end of 2022. However when Intel talks about specific products, they usually mean it ramps and launches in ~1H. For example, Alder Lake ramp on Intel 7 was claimed for a 2H 2021 ramp, and launched by the end of 2021. Intel when specifically referring to MTL always talked about a 2H 2023 ramp as well, and they still claim it will launch by the end of 2023.
Another potentially significant detail is that when Pat said ARL product ramp late 2024, meaning it should launch early 2025 most likely, is that he also claims ARL is still on track, so that means there's a really good chance there is a TSMC 3nm version of ARL coming out sometime 2024. Because Intel 20A just sounds like it is not ready.
In short Pat just gave a lot more credence to the ARL dual sourcing on Intel 20A and TSMC 3nm rumors IMO.
 
So it looks like MTL (Intel 4) and RPL-R (Intel 7) end of 2023, ARL (TSMC 3nm) mid/end of 2024, GNR+SRF (Intel 3) mid/end 2024, LNL (TSMC 3nm?) end of 2024/early 2025, ARL (Intel 20A) mobile early/mid 2025.
~2 products around every ~1H for Intel starting from end of 2023.
5 nodes, from Intel 7 to Intel 20A, in a 2 year span.
7 completely different designs in 2 years.
... if Intel pulls this off, it would be a miracle.
 
DrMrLordX said:
I'm fairly certain that someone has run CBR23 on a 12900k with the e-cores disabled. Comparing the results of that run with the Sapphire Rapids Xeon W should be educational.
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I already wrote this:
I just checked, 1 Raptor core two threads at 3500 MHz does 1820 points at 7W. 56 of them would make 102 000 points at 400W. If they ran at 2600 MHz, they would make 75 700 points.
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Alder and Raptor cores have nearly identical performance.
 
jpiniero said:
The issue is likely more 10 nm (and that they made the cores super big) than the disagreggation.
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It can't be 10nm, my 12700K does ~17.5K points in CB23 with 8+0 config and PL1=PL2=125W. Cores oscillate between 4.2 and 4.3 GHz, VCore is around 1,15V (as opposed to 1V for 4.2Ghz that I saw being discussed earlier for SPR). If I force the cores to run at base speed, then the CPU scores 14K+ while using 70W. So a hypothetical 32 core ADL chip using older gen Intel 7 lithography, could score close to 70K in CB23 and use exactly 500W. A 56 core ADL could still use 500W and score 90-100K in CB23.

So it's either a problem with the core, or a problem with moving data around.
 
The problem with Sapphire Rapids can simply be attributed to bad execution. Delays = Bad products. It gets delayed because it doesn't meet the original goals or messed up along the way. It never gets delayed because they want to make it better. It gets delayed because it sucks and you need to fix it.

The original Xeon Phi was a 215W part reaching 3.3TFlop DP FP. It got delayed 6 months and it ended up being 230W reaching 3TFlop DP FP. 10% here, 10% there, and silicon has variation so if you don't do it well, what looks like the same product doesn't at the end.
 
I just noticed that that 142W idle power is just for high performance power management in Windows, normal balanced setting causes "just" 50W power draw, which is comparable with Threadripper.
 
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