Discussion Intel current and future Lakes & Rapids thread

[DrMrLordX]

Come on, let's give credit where it's due. IF ADL does deliver 20-30% increase in ST performance the Intel's lineup will be very competitive where it really matters.

It really depends on what it's competing against. Zen3 + stacked L3? Might be a contest. Zen4? Nah. As it stands, AMD won't bother telling anyone when either of those chips will launch, so I guess the only matchup we can hope for is Vermeer vs. Alder Lake-S.

Think ADL-S 6+0 versus 5600X, or ADL-S 8+SOMETHING versus 5800X.

The only reason this seems appealing is that it's been so hard to buy those chips for so long, that people are still picking them up like they're the next big thing, even if they've been the next big thing for over eight months now. Scarcity sure distorts the picture.

Oh well, long Q2&Q3 ahead...

Yeah, agreed there.

The 5950x is an HEDT chip by every measure.

HEDT chips are 64c/128t monsters now. Wake up.

The fact that AMD wanted to artificially maintain multithreaded superiority when Intel started releasing 8 core chips into the mainstream segment is not lost on some of us.

There was nothing artificial about it.

AND, I doubt this chip is going to exhibit clear single-threaded weakness.

You mean like the 5950x, which doesn't exhibit "clear single-threaded weakness"?

 

[Zucker2k]

You mean like the 5950x, which doesn't exhibit "clear single-threaded weakness"?

The 5950x is considered the top dog on mainstream x86 eco-system. Is it the top dog in single-thread or few threads? I mean it'll cost you $849.00 on newegg right now for your niche throughput desktop computing.

 

[DrMrLordX]

The 5950x is considered the top dog on mainstream x86 eco-system. Is it the top dog in single-thread or few threads?

Yes.

 

[Carfax83]

It really depends on what it's competing against. Zen3 + stacked L3? Might be a contest. Zen4? Nah. As it stands, AMD won't bother telling anyone when either of those chips will launch, so I guess the only matchup we can hope for is Vermeer vs. Alder Lake-S.

By the time Zen 4 comes out, Raptor Lake will be out and from what MLID has said, it's projected to be a significant IPC boost, but not as much as from Willow Cove to Golden Cove. If Intel can squeeze another 10-15% out of Raptor Lake, it will be competitive with Zen 4 since they got a big boost with Golden Cove to put it well above Zen 3 and Zen 4 is rumored to have around 20-30% IPC gain over Zen 3.

As for Zen 3 enhanced, I'm going to wait for more benchmarks to leak so I can ascertain how well Alder Lake performs in other applications before I come to any conclusion as to how it will stack up.

If Cinebench is any indication though, Alder Lake is a beast!

 

[Asterox]

The 5950x is considered the top dog on mainstream x86 eco-system. Is it the top dog in single-thread or few threads? I mean it'll cost you $849.00 on newegg right now for your niche throughput desktop computing.

The price reflects, Intel does not have a competitive cpu in that price segment.

Alder Lake can change that, but only if 8+8 Alder Lake has good CPU power efficiency.

 

[nxre]

The more leaks come out the more Gracemont seems like the most important piece of the puzzle for Alder Lake. Now we only need power numbers to see if Intel has managed to beat ARM at their own game or if Gracemont is not really as small of a core as imagined.
Still, Alder Lake is shaping up to be a fantastic release. 8big+8small matching 16big in multicore is absolutely amazing and not something I would consider Intel to be able to pull off just a few months ago. I am, as many have said, cautiously optimistic.

 

[JoeRambo]

If Intel can squeeze another 10-15% out of Raptor Lake, it will be competitive with Zen 4 since they got a big boost with Golden Cove to put it well above Zen 3 and Zen 4 is rumored to have around 20-30% IPC gain over Zen 3.

I think it is safe to say with recent leaks, that Intel has huge potential for core performance in Alder Lake - both small cores and big cores. So next logical step would be to add more small cores and work on uncore to properly feed this monster.
And guess what? They are doing just that: doubling GMT cores to 16 with vague improvements to hybrid cores AND "improved CPU cache for gaming".

One has to wonder how it will be improved, Alder Lake already has 30MB of L3, if we add 2 more slices of 4 GMT cores, that is 36MB of L3 already.

 

[jpiniero]

The more leaks come out the more Gracemont seems like the most important piece of the puzzle for Alder Lake. Now we only need power numbers to see if Intel has managed to beat ARM at their own game or if Gracemont is not really as small of a core as imagined.

I def don't expect Gracemont to be that small. Golden Cove is going to be huge so you have to take that into consideration how big the cluster is.

 

[coercitiv]

If only the ghosts of the Mont and the Well families could see this: the ridiculed, the marginalized, the forgotten Atom is now proclaimed as the new hope of the Empire. It's the Middle Ages all over again. /s

 

[eek2121]

No it is not HEDT CPU.

For example, old Ryzen 7 1800X is not HEDT CPU.As we now i7 6900K is HEDT CPU, and everything else is history.

HEDT CPU has quad-channel DDR4 memory, and much more PCIE lanes vs classic Desktop CPU.

Product Specifications

quick reference guide including specifications, features, pricing, compatibility, design documentation, ordering codes, spec codes and more.

ark.intel.com

https://www.amd.com/en/products/cpu/amd-ryzen-7-1800x

At the end, the most important is CPU price=performance.CPU Power efficiency is also very important detail.

HEDT is a marketing term. It means nothing.

The 5950x is considered the top dog on mainstream x86 eco-system. Is it the top dog in single-thread or few threads? I mean it'll cost you $849.00 on newegg right now for your niche throughput desktop computing.

I own one. 5.1 ghz (single core) Zen 3 is fantastic. AMD knocked it out of the park.

The more leaks come out the more Gracemont seems like the most important piece of the puzzle for Alder Lake. Now we only need power numbers to see if Intel has managed to beat ARM at their own game or if Gracemont is not really as small of a core as imagined.
Still, Alder Lake is shaping up to be a fantastic release. 8big+8small matching 16big in multicore is absolutely amazing and not something I would consider Intel to be able to pull off just a few months ago. I am, as many have said, cautiously optimistic.

I def don't expect Gracemont to be that small. Golden Cove is going to be huge so you have to take that into consideration how big the cluster is.

Gracemont is a quarter of the size of Golden Cove while offering much of the performance of modern skylake.

Gracemont’s successor may very well make the cove cores obsolete.

Also, who needs hyperthreading when you can have 4x the number of cores? Yes I know the mont cores will get bigger, but they will still be smaller than cove at the end of the day.

 

[jpiniero]

Gracemont is a quarter of the size of Golden Cove while offering much of the performance of modern skylake.

There haven't been any rumors about the size of Gracemont. That it's a quarter of the size of Golden Cove is just a projection. And if Golden Cove is gigantic, even a quarter of the size might be really big compared to ARM.

 

[biostud]

Hopefully the rumors are true. Competition is good news for the consumer.

 

[eek2121]

There haven't been any rumors about the size of Gracemont. That it's a quarter of the size of Golden Cove is just a projection. And if Golden Cove is gigantic, even a quarter of the size might be really big compared to ARM.

There was a flurry of tweets that went arount Twitter several months ago that claimed 4 gracemont cores fit in the space of one Golden Cove core.

 

[dullard]

If only the ghosts of the Mont and the Well families could see this: the ridiculed, the marginalized, the forgotten Atom is now proclaimed as the new hope of the Empire. It's the Middle Ages all over again. /s

As the Anandtech website likes to say "there are no bad CPUs there are only bad prices". In Atom's case, it wasn't necessarily as much bad prices as Atom was put into the wrong products.

The netbook devices were disasters for many reasons. Part of that certainly was because Atom was not powerful enough for people's expectations. You can't put a 0.65 W to 10 W chip into a laptop and have people think it performs like a 25 W to 65 W mobile CPU. But Atom's real downfall was mostly because they were put into products which were made to be as cheap as humanly possible. No one really wanted a cheap plastic laptop-like device with miniscule ugly screen, keyboard that was too small to be usable in any long term way, and no real ability to install your software (usually no optical drive and often no free hard drive space). Those products should never have been made in the first place. No computer company wanted to put out a product to compete with their cash-cow laptops that were selling well over $1000 at the time.

A low cost, low power CPU that runs native x86 programs is great for niche uses even if the CPU performance is low. Mining for example likes sub $40 CPUs, and some Atom chips were sub $6. Industrial sensors, IOT, fanless computers, etc all have great niche Atom uses. But, instead, we got stuck with terrible netbooks that couldn't do much of anything.

 

[Hulk]

What? Cinebench R20 saturates all threads with a full load, you don't have to worry about scheduling at all. You don't have to allocate anything to any specific cores at all either.

Got it. But just confirm the following scenario isn't possible.

Could some threads present heavier workloads than others? If so then it would not be optimal for Gracemont cores to be assigned to these threads as they would could be bottlenecks. In addition, Golden Cove cores assigned to "light compute" threads would mean they could be switching among threads like mad, again not optimal.

That's what I was alluding to. Loading all cores is not the same as loading all cores in the most efficient manner. Task switching is a "load," but one that doesn't do any productive work.

 

[dullard]

Got it. But just confirm the following scenario isn't possible.

Could some threads present heavier workloads than others? If so then it would not be optimal for Gracemont cores to be assigned to these threads as they would could be bottlenecks. In addition, Golden Cove cores assigned to "light compute" threads would mean they could be switching among threads like mad, again not optimal.

That's what I was alluding to. Loading all cores is not the same as loading all cores in the most efficient manner. Task switching is a "load," but one that doesn't do any productive work.

Think of it this way, suppose there are 100 bricks to move from one side of a room to the other. Suppose you have two 3-year-olds and two healthy able adults. You have many different ways to divvy up that workload.

Ordered from slowest to fastest:
1) Assign 25 bricks to each person. This is pretty sub-optimal, as it doesn't include knowledge that we already know: most likely the adults will just sit around idle for quite a while waiting for the children to move the bricks.
2) Assign 50 bricks to each adult. The children will sit idle, but they wouldn't likely do much anyways, so it is faster than #1.
3) Assign maybe 5 bricks to each child and 45 bricks to each adult. This is getting pretty close to what is likely to be the most optimal solution. But it includes a lot of difficult assumptions. Do we really know how many more bricks an adult will move compared to a child?
4) Don't assign bricks, just let them go, whenever someone has a free hand, they pick up another brick.

We'd always love to go with #4. But that just isn't how workloads function in real life. What if the bricks had to be stacked in a specific order, like when you are renovating the Athen Parthenon and want to put the bricks back in their original locations? Having an adult bring a brick before a child brings a lower brick suddenly means the adult has to sit and wait, possibly quite long time until the right brick is put down.

I'm not familiar enough with Cinebench to know for sure, but I think it is pretty close to #4. Rendering with ray tracing tends to not care about order. You just need to trace a bunch of rays and combine the end result. Cinebench is useful for benching that type of workload, but many software programs aren't dividable like that. In these cases, we want to go with #3, but that requires an interaction of information from both software and hardware. What if one child needs to be attended to by an adult? In that case, we want secret option #5: 5 bricks to each child, 20 to one adult to allow that adult some time with the children, and 70 to the other adult. But, to know that, we need advanced information from the hardware, the operating system, and the programmers themselves. The real debate is how far along is this cooperation.

 

[JoeRambo]

I'm not familiar enough with Cinebench to know for sure, but I think it is pretty close to #4. Rendering with ray tracing tends to not care about order. You just need to trace a bunch of rays and combine the end result. Cinebench is useful for benching that type of workload, but many software programs aren't dividable like that. In these cases, we want to go with #3, but that requires an interaction of information from both software and hardware. What if one child needs to be attended to by an adult? In that case, we want secret option #5: 5 bricks to each child, 20 to one adult to allow that adult some time with the children, and 70 to the other adult. But, to know that, we need advanced information from the hardware, the operating system, and the programmers themselves. The real debate is how far along is this cooperation.

It is of type - assign adults and children 5 bricks each, but adults complete round trip much faster and receive next portion. But in the end of brick pile, there is a problem it has to wait for children to complete their trip with last portion.

OS scheduler has a real conundrum - should it take those 5 bricks from child and give it to the adult that is now idle ? Should it do so if child has only 5 meters left? What about 50 meters left? What if brick handover is tricky ( as in cold versus hot data/instruction caches, L2 slice )? What if children work for bottle of coke and adults needs wage in dollars to pay their power bills?

 

[HurleyBird]

Should it do so if child has only 5 meters left? What about 50 meters left?

The scheduler isn't going to know the amount of work remaining anyway.

 

[JoeRambo]

The scheduler isn't going to know the amount of work remaining anyway.

Yeah, but the child can provide feedback to the OS: "Hey, i am carrying heavy bricks for what is 45 meters now, help" - and OS can decide to move the heavy load from child to adult, even if there are 5 meters left, cause on average it will benefit.
This way it can react to characteristics of workload dynamically.

 

[DrMrLordX]

By the time Zen 4 comes out, Raptor Lake will be out and from what MLID has said, it's projected to be a significant IPC boost, but not as much as from Willow Cove to Golden Cove. If Intel can squeeze another 10-15% out of Raptor Lake, it will be competitive with Zen 4 since they got a big boost with Golden Cove to put it well above Zen 3 and Zen 4 is rumored to have around 20-30% IPC gain over Zen 3.

I'm just gonna say, that's a rosy projection, and leave it at that.

 

[coercitiv]

Yeah, but the child can provide feedback to the OS: "Hey, i am carrying heavy bricks for what is 45 meters now, help" - and OS can decide to move the heavy load from child to adult, even if there are 5 meters left, cause on average it will benefit.
This way it can react to characteristics of workload dynamically.

The way Intel addressed this issue with Lakefield was that user initiated request have priority (foreground vs. background split). After that you have a second order of business, which is to optimize for total task energy or total task time. Therefore, when CB20 is a foreground task and system profile is something like Balanced/Performance, the adults will definitely be tasked to relieve the kids of the last bricks. But then again, this is nothing new, we're reinventing the wheel here because somebody is convinced there's a big gain to be had from scheduler optimization, the suggestion @Hulk made implied some type of profiling actually.

Here's a mental image that may help some realize this problem isn't that novel: think of the small cores as big cores continuously running a phantom thread which takes 25% of core execution time. Should a "traditional" scheduler not be able to properly assign working threads on such a CPU?!

 

[dullard]

Here's a mental image that may help some realize this problem isn't that novel: think of the small cores as big cores continuously running a phantom thread which takes 25% of core execution time. Should a "traditional" scheduler not be able to properly assign working threads on such a CPU?!

Depends. Would assigning the work to the other thread give the big core enough cool down time to turbo longer (alder lake) or not (rocket lake)?

 

[blckgrffn]

Haha, pricing on CPUs, grouching about $850 chips that are gorillas. You guys forget this type of pricing?



I'll even do the inflation adjusted math there. In 2006, you paid $1,000 for about an 8% (head math) uplift in frequency, no other benefits. This is a ~100% price premium over the next available SKU.

That's ~1,332 in todays dollars, or a difference of about $650 for a final cpu frequency bump.

Right now you pay way less for the leading Intel SKU and bumping from AMDs second best desktop chip (5900x to 5950x) costs you $250 and you get a smidge of frequency plus four full cores for your trouble.

Competition is good. That's what I am saying.

And saying a CPU is not a "desktop" CPU because it costs north of some arbitrary number is silly. Like saying a 3090 is a scientific part and not a gaming GPU "because it costs over $2,000". Different people obviously are going to be comfortable with different price limits. I couldn't imagine paying more than $400 for a CPU so I've had a 3930k and now a 5800x.

 

[eek2121]

Haha, pricing on CPUs, grouching about $850 chips that are gorillas. You guys forget this type of pricing?

View attachment 47535

I'll even do the inflation adjusted math there. In 2006, you paid $1,000 for about an 8% (head math) uplift in frequency, no other benefits. This is a ~100% price premium over the next available SKU.

That's ~1,332 in todays dollars, or a difference of about $650 for a final cpu frequency bump.

Right now you pay way less for the leading Intel SKU and bumping from AMDs second best desktop chip (5900x to 5950x) costs you $250 and you get a smidge of frequency plus four full cores for your trouble.

Competition is good. That's what I am saying.

And saying a CPU is not a "desktop" CPU because it costs north of some arbitrary number is silly. Like saying a 3090 is a scientific part and not a gaming GPU "because it costs over $2,000". Different people obviously are going to be comfortable with different price limits. I couldn't imaging paying more than $400 for a CPU so I've had a 3930k and now a 5800x.

I paid under $2,000 for my 3090. The MSRP was $1,700 for my EVGA one and that is what I paid. I also bought a 1950x for $999 and a 5959x for $860 (after tax). My 1080ti was $800.

I have no problems paying top dollar for premium parts.

 

[dullard]

Haha, pricing on CPUs, grouching about $850 chips that are gorillas. You guys forget this type of pricing?

Competition is good. That's what I am saying.

Competition is good, but competition doesn't have that much to do with pricing. A duopoly (two companies competing) generally drops prices about 20% compared to a monopoly. It is something, but not a whole lot. That 20% drop vanishes if companies can have marketable differences.

I remember the Intel/AMD MHz wars. Basically the same chips, just kept bumping up the MHz every month or so. Great increases in speed, almost identical competitors. What happened to prices? They went up ~$100/month. What really controls prices? Demand. That MHz war happened at the Y2K transition when demand skyrocketted.

AMD:


Intel: