Discussion Intel current and future Lakes & Rapids thread

[Asterox]

Are you a human?

www.newegg.com

New Acer with Jasper Lake Celeron N4500 is out.

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ark.intel.com

Price seems high, $389.
I paid $230-250 for my Zen 3020e and 3050e laptops, and the 3050e is 1080P.
Curious how performance compares to Zen. But Intel is still a NO-BUY for me, until the add something similar to AMD's VSR into their drivers. I much prefer an AMD 3050e APU-based laptop with a 1080P screen that I can actually crank up to 4k UHD effectively.

Celeron N4500 is 2/2 CPU vs Athlon Silver 3050e is 2/4 CPU.

 

[lobz]

Celeron N4500 is 2/2 CPU vs Athlon Silver 3050e is 2/4 CPU.

Point being?

 

[coercitiv]

You can't have it both ways, either it will offer performance similar to skylake or it won't. I'm inclined to think it will.

It's Skylake performance per clock that people agreed Gracemont can reach, not Skylake performance!

That Alder Lake ES produced a GB5 score that only 4.5Ghz+ Skylake cores can get. In order for 8 Gracemont @ 3.4-3.6Ghz to get the same or better scores as 8 Skylake cores @ 4.5Ghz+, the difference in IPC would amount to almost 40%. This is Golden Cove range.

 

[eek2121]

It's Skylake performance per clock that people agreed Gracemont can reach, not Skylake performance!

That Alder Lake ES produced a GB5 score that only 4.5Ghz+ Skylake cores can get. In order for 8 Gracemont @ 3.4-3.6Ghz to get the same or better scores as 8 Skylake cores @ 4.5Ghz+, the difference in IPC would amount to almost 40%. This is Golden Cove range.

Incorrect. Core i5 6500, 3.2 - 3.6 GHz, 945/3277: Gigabyte Technology Co., Ltd. Z170MX-Gaming 5 - Geekbench Browser

 

[AMDK11]

Due to the fact that there are good pictures of the x86 core structure, I have scaled the x86 GoldenCove and x86 CypressCove (SunnyCove) structures as far as possible, I compared both and ... I have a strange feeling that Golden is hardly bigger at all :/ Either all proportional structures have been expanded or there are only minor changes and optimizations. Strange.

PS Anyone making a similar comparison?

 

[scineram]

The i5 6500 is a 4 core, 4 thread CPU running at 3.2-3.6 ghz. Previous rumors HAVE claimed the new cores will have performance similar to skylake. We also have rumors that say ES2 was running at 3.4 ghz. AnandTech has the 6500 as having a GB5 single core speed of 1001 and a multicore speed of 3372. You can't have it both ways, either it will offer performance similar to skylake or it won't. I'm inclined to think it will. There is no reason Intel can't make that kind of performance leap.

Apparently Razer canceled my preorder this morning for the 11800h system. Intel just lost a sale. I needed a laptop before July, so I bought the razer blade advanced 14 with a 5900hx and a 3070 off Amazon. It will be here later this week.

Why did that happen? Does Tiger Lake have supply issues?
I think you’re better off with Ryzen.🤣

 

[eek2121]

Why did that happen? Does Tiger Lake have supply issues?
I think you’re better off with Ryzen.🤣

Support said they couldn’t give a reason. They had one job…

EDIT: No, Tiger Lake does not have supply issues. I could buy another brand hand have it by tomorrow, but most are too heavy.

 

[IntelUser2000]

Due to the fact that there are good pictures of the x86 core structure, I have scaled the x86 GoldenCove and x86 CypressCove (SunnyCove) structures as far as possible, I compared both and ... I have a strange feeling that Golden is hardly bigger at all :/ Either all proportional structures have been expanded or there are only minor changes and optimizations. Strange.

PS Anyone making a similar comparison?

The only Golden Cove shot is from Sapphire Rapids, and it's 10nm. Cypress Cove is 14nm.

If you compare Golden Cove core in SPR to Sunny/Willow Cove in Ice/Tigerlake, you'll see that Golden Cove is noticeably larger.

It couldn't have been proportionally expanded because SPR adds AMX which adds quite a bit of die space and it also has full AVX-512 FMA units. Sapphire Rapids also has 2MB L2 cache which is larger than 1.25MB on Willow Cove.

 

[AMDK11]

The thing is, I know it I didn't take into account the second 512bit unit (analogous to Skylake-SP), L2 2MB (2-Way / 256KB) (whose structure is different from L2 in WillowCove (4- Way / 256KB)) and all the more L3 with logic just above L1D 48KB.

I took a closer look at the basic x86 logic along with L1D and L1I.

Of course, you can see redesigned and potentially expanded places.

GoldenCove's single core snapshot on Twitter is that every x86 core has L3 over L1D, not under Front-End.

 

[jpiniero]

Oh this is good. Sapphire Rapids aparently has mirrored dies because of DDR and PCIe placement routing. You get two of each.

 

[uzzi38]

Oh this is good. Sapphire Rapids aparently has mirrored dies because of DDR and PCIe placement routing. You get two of each.

Yeah, mentionned it a while back here. Olrak's diagram does a great job of showing the issue:

https://twitter.com/x/status/1405131713706037252

 

[majord]

What's the reasoning behind thinking these GB ST scores are the gracemont core ?

 

[IntelUser2000]

What's the reasoning behind thinking these GB ST scores are the gracemont core ?

My reasons:

Not saying all of them are, but those in the 1000 range make it plausible, and Tremont already gets 730. See early Lakefield ST leaks were abysmal. Now it's bad, but back then it was abysmal. It means it was running on the Tremont cores. In Lakefield, the Tremont cores are limited in clock speeds even when only 1 core is running.

Also user-submitted benchmarks like Geekbench are notoriously unreliable. This is why we hope reviewers do comprehensive tests covering many scenarios as possible with many applications as possible. Too bad Geekbench 5 doesn't have an easy way to sort from low to high score like GB4.

Add to that the early nature of a hybrid core on Alderlake. Who knows what's running on what?

 

[repoman27]

RetiredEngineer® @chiakokhua tweeted this a few days ago, and I was wondering if anyone remembered seeing it before:

https://twitter.com/x/status/1404101126358663176

I was curious about the source and some idea of how old it was. My search attempts came up with nada.

All the roadmap leaks seem to point to a 56-core SKU at the top of the stack, but we know SPR XCC is based on four dies that each have 15 cpu core tiles plus an IMC tile and I/O cap. The theory being that each die will have at least one core disabled because... yields? I have a seriously hard time believing that the Intel that is currently touting a fully enabled 40-core monolithic die manufactured on 10+ won't try to bring to market a product with four fully enabled 15-core tiles on 10+++ a year later. Sure it might be thin-binned like the 8380 and/or liquid-cooled like the 8368Q, but it will almost certainly see the light of day. Unless there's some other technical reason that I'm just missing...

I was also contemplating the 34C MCC based platform indicated in that tweet. If we add another column to the XCC die—three more CPU core tiles and another IMC tile—we end up with an 18-core die with four memory channels. A two die package would have up to 36 cores (or 34 with at least one core disabled on each die) and still have 8-channel memory. An 18-core, 4-channel HEDT or workstation product would also be possible using a single die. The whole stack, LCC to XCC, is still covered by just three tape-outs: MCC tile, XCC left tile, and XCC right tile. Ironically though, the MCC tile will be larger and have more cores than the XCC tiles.

Also, here are some links to the recent Sapphire Rapids die-shot posts on Bilibili from YuuKi_AnS and Big IC Micro World, which probably include better quality images than other sources:

大IC微世界 Bilibili 2021-06-12
結城安穗-YuuKi_AnS Bilibili 2021-06-12

 

[eek2121]

What's the reasoning behind thinking these GB ST scores are the gracemont core ?

Gracemont has been widely rumored to have Skylake levels of performance. Skylake (Core i5 6500) performs similarly to current public GB5 scores while having similar clocks.

My reasons:

Not saying all of them are, but those in the 1000 range make it plausible, and Tremont already gets 730. See early Lakefield ST leaks were abysmal. Now it's bad, but back then it was abysmal. It means it was running on the Tremont cores. In Lakefield, the Tremont cores are limited in clock speeds even when only 1 core is running.

Also user-submitted benchmarks like Geekbench are notoriously unreliable. This is why we hope reviewers do comprehensive tests covering many scenarios as possible with many applications as possible. Too bad Geekbench 5 doesn't have an easy way to sort from low to high score like GB4.

Add to that the early nature of a hybrid core on Alderlake. Who knows what's running on what?

It does. For multicore performance, add &sort=multicore_score to the end of the URL. For single core performance, add &sort=score to the end of the URL. Both options assume you already have some parameters following a question mark.

 

[Exist50]

I was also contemplating the 34C MCC based platform indicated in that tweet. If we add another column to the XCC die—three more CPU core tiles and another IMC tile—we end up with an 18-core die with four memory channels. A two die package would have up to 36 cores (or 34 with at least one core disabled on each die) and still have 8-channel memory. An 18-core, 4-channel HEDT or workstation product would also be possible using a single die. The whole stack, LCC to XCC, is still covered by just three tape-outs: MCC tile, XCC left tile, and XCC right tile. Ironically though, the MCC tile will be larger and have more cores than the XCC tiles.

Here's another thought. Consider a monolithic 34c MCC die. It would be huge, yes, but doable, and reasonably bin-able to <=32c high volume SKUs, without fussing with SNC or the like.

 

[insertcarehere]

Here's another thought. Consider a monolithic 34c MCC die. It would be huge, yes, but doable, and reasonably bin-able to <=32c high volume SKUs, without fussing with SNC or the like.

Existing 40-core ice lake server dies are (supposedly) approx 640mm^2, if SPR with less cores (half of which should be gracemont cores which take up nothing in size) isn't significantly smaller then Intel desperately needs better engineers.

 

[diediealldie]

Here's another thought. Consider a monolithic 34c MCC die. It would be huge, yes, but doable, and reasonably bin-able to <=32c high volume SKUs, without fussing with SNC or the like.

A single SPR tile uses ~480mm^2 with only 15 cores. This is equivalent to the size of a hypothetical 30-core Ice lake server chip. Either Ice lake server chip has a very bad yield(So that they negate low yield by using smaller tiles) or SPR is super nice compared to Ice lake to justify this enormous silicon uses.

 

[naukkis]

Jim Keller announced way back upcoming Intel cpu's that are huge - 800 OOE window and so on. So maybe Golden Cove is one of those and CPU core itself is huge. Intel of course expects it's performance to be also huge - but it might not be. But cpu cores of that big explains why there's only 15 of them in chiplet.

 

[repoman27]

Existing 40-core ice lake server dies are (supposedly) approx 640mm^2...

A single SPR tile uses ~480mm^2 with only 15 cores...

Ice Lake-SP XCC 40C die size is 624 mm².

A single 15C tile for Sapphire Rapids-SP XCC is 426 mm².

Those are my measurements based on the highest resolution wafer and package shots I could find. Feel free to check my work, but I'm pretty sure those are as close to accurate as you're gonna get. The internet seems intent on arbitrarily inflating the size of these dies, even if only by a small amount.

 

[scineram]

Yeah, mentionned it a while back here. Olrak's diagram does a great job of showing the issue:

https://twitter.com/x/status/1405131713706037252

So they need to manufacture 2 chips. But hard it was to design them? Can they just do one and then push the flip button? Or would that make it big endian?

 

[SAAA]

Ice Lake-SP XCC 40C die size is 624 mm².

A single 15C tile for Sapphire Rapids-SP XCC is 426 mm².

Those are my measurements based on the highest resolution wafer and package shots I could find. Feel free to check my work, but I'm pretty sure those are as close to accurate as you're gonna get. The internet seems intent on arbitrarily inflating the size of these dies, even if only by a small amount.

Even using those accurate measurements it seems silly to have an 80% increase in area per core on average. I hope whatever inflated size that much is worth it.

Jim Keller announced way back upcoming Intel cpu's that are huge - 800 OOE window and so on. So maybe Golden Cove is one of those and CPU core itself is huge. Intel of course expects it's performance to be also huge - but it might not be. But cpu cores of that big explains why there's only 15 of them in chiplet.

Yeah, could be a reason, but at that point I'd really expect a lot more than projected 20% gains, I mean even Icelake over Skylake gets +19% IPC for +38% area, it seems weird they need almost twice that again to reach the same increase. It would be just better to place 80% more Icelake cores otherwise...

 

[jpiniero]

Yeah, could be a reason, but at that point I'd really expect a lot more than projected 20% gains, I mean even Icelake over Skylake gets +19% IPC for +38% area, it seems weird they need almost twice that again to reach the same increase. It would be just better to place 80% more Icelake cores otherwise...

Are you accounting for the IO changes/PCIe5/CXL and then AMX added to the core?

 

[DrMrLordX]

Existing 40-core ice lake server dies are (supposedly) approx 640mm^2, if SPR with less cores (half of which should be gracemont cores which take up nothing in size) isn't significantly smaller then Intel desperately needs better engineers.

Intel doesn't seem to want to use *mont cores in their server/workstation CPUs. Probably because they want full AVX-512 available without complication for that customer base. Among other things.

Either Ice lake server chip has a very bad yield(So that they negate low yield by using smaller tiles) or SPR is super nice compared to Ice lake to justify this enormous silicon uses.

IceLake-SP apparently did have awful yields for awhile. It remains to be seen how many IceLake-SP and Sapphire Rapids chips they can provide to the market.

 

[Mopetar]

A single SPR tile uses ~480mm^2 with only 15 cores. This is equivalent to the size of a hypothetical 30-core Ice lake server chip. Either Ice lake server chip has a very bad yield(So that they negate low yield by using smaller tiles) or SPR is super nice compared to Ice lake to justify this enormous silicon uses.

Doubtful the yields are bad. They're just disabling one core per chip/tile, which they might want to do even if it isn't bad in order to hit clock speeds or voltage targets for the chip more easily. Even if all of your silicon is functional, not all of it is going to perform at the desired level.

The reality is that they need to use that much silicon because AMD is going to be making 128-core server chips soon and I think more and more businesses are waking up to the fact that Intel isn't the only game in town anymore.