Discussion Intel current and future Lakes & Rapids thread

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Magic Carpet

Diamond Member
Oct 2, 2011
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There is also the possibility that most initial modules will be JEDEC only and the XMP versions will come during later months
GEIL

The GeIL DDR5 memory specification starts at 4800MHz with the sub-timing latencies of CL40-40-40 at 1.1 volts. The overclocking products are also under development, including 6000MHz CL32-36-36, 6400MHz CL32-36-36, 6800MHz CL36-44-44, and 7200MHz CL36-44-44, and will be available with non-RGB product versions at the same time.
 
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DrMrLordX

Lifer
Apr 27, 2000
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If latencies are a strong indicator of volumes and availability, then sure! /s

Article says availability in Q4 2021. In what quantities we don't know, but if enthusiast DIMMs are already going to be available, it's likely that green PCB OEM sticks should also be in-channel by then as well.
 

uzzi38

Platinum Member
Oct 16, 2019
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I think all of the leaked benchmarks have been using DDR5 or at least are saying it's using DDR5. Intel could end up not officially supporting DDR4 in the end but that seems unlikely.
Nobody's talking about just flat out not supporting DDR4/DDR5, but what is available on launch. I'm certainly not trying to insinuate one would be dropped in favour of the other at least - I expect both to be available.
 

coercitiv

Diamond Member
Jan 24, 2014
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Hardware Unboxed tested TGL H45 and looked at performance with different TDP settings and boost disabled. This is a missing piece of the puzzle which shows that TGL H really likes more power, as increasing TDP towards desktop levels helps TGL catch up in terms of efficiency.

It's almost as if TGL H45 was meant to be TGL-S :p

tgl-scaling.png
 

firewolfsm

Golden Member
Oct 16, 2005
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This is the first data we've seen for the 10SF process using more power. It seems it scales well and can clock high. I would expect Intel to keep the single thread crown w/r/t alder lake vs. Ryzen 6xxxx.
 

dullard

Elite Member
May 21, 2001
25,055
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What a huge relief that the tech doesn't rely on RGB illumination to work. 🤣
Even worse than not relying on RGB, RGB actively makes the technology perform at a lower level. We spend eons debating in this very thread about 1 Watt here and 1 Watt there, then people dump a bunch of power and heat into their individual components to have annoying lights. Yes, one LED doesn't use a massive amount of power. But every LED on every component takes away power from the CPU and adds heat to the system.
 

eek2121

Platinum Member
Aug 2, 2005
2,930
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Even worse than not relying on RGB, RGB actively makes the technology perform at a lower level. We spend eons debating in this very thread about 1 Watt here and 1 Watt there, then people dump a bunch of power and heat into their individual components to have annoying lights. Yes, one LED doesn't use a massive amount of power. But every LED on every component takes away power from the CPU and adds heat to the system.

I will make sure to take a pic of my super
gamer RGB build and share it here just for you.
 
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eek2121

Platinum Member
Aug 2, 2005
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Hardware Unboxed tested TGL H45 and looked at performance with different TDP settings and boost disabled. This is a missing piece of the puzzle which shows that TGL H really likes more power, as increasing TDP towards desktop levels helps TGL catch up in terms of efficiency.

It's almost as if TGL H45 was meant to be TGL-S :p

View attachment 44675

I’ve said it before, but Tiger Lake would make an awesome desktop chip. Give it a 125W TDP and let it rip.
 
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Asterox

Golden Member
May 15, 2012
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This is the first data we've seen for the 10SF process using more power. It seems it scales well and can clock high. I would expect Intel to keep the single thread crown w/r/t alder lake vs. Ryzen 6xxxx.

It is not all alone 10SF, it is combination of Intel CPU arhitecture+10nmSF.

Alder Lake+10nmSF, it will be power hungry even more vs current Rocket Lake on 14nm.

 

eek2121

Platinum Member
Aug 2, 2005
2,930
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It is not all alone 10SF, it is combination of Intel CPU arhitecture+10nmSF.

Alder Lake+10nmSF, it will be power hungry even more vs current Rocket Lake on 14nm.


Your second statement is incorrect.

EDIT:

  1. Tiger Lake has 90% of the performance of rocket lake while using 30% of the power.
  2. Alder Lake ES has a PL2 of 228W
  3. Alder Lake has AVX-512 disabled. AVX-512 is one of the big reasons recent Intel chips use so much juice.
 
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Ajay

Lifer
Jan 8, 2001
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It is not all alone 10SF, it is combination of Intel CPU arhitecture+10nmSF.

Alder Lake+10nmSF, it will be power hungry even more vs current Rocket Lake on 14nm.

IIRC, Alder Lake is on ESF, perhaps it offers a better perf/power ratio? Or, it could just be a yield improvement.
 
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Ajay

Lifer
Jan 8, 2001
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Nobody's talking about just flat out not supporting DDR4/DDR5, but what is available on launch. I'm certainly not trying to insinuate one would be dropped in favour of the other at least - I expect both to be available.
Yeah, all the high end enthusiast boards will be DDR5. Alder Lake will need the extra bandwidth to compete with Vermeer.
 

eek2121

Platinum Member
Aug 2, 2005
2,930
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Yeah, all the high end enthusiast boards will be DDR5. Alder Lake will need the extra bandwidth to compete with Vermeer.

Intel Corporation AlderLake-P LP4x RVP

That may indicate LPDDR4X support.

EDIT:

All other known platform names:
  • Intel Corporation AlderLake-S ADP-S DDR5 UDIMM CRB
  • Intel Corporation ADL-S ADP-S DDR5 UDIMM OC CRB
  • Intel Corporation AlderLake-S ADP-S DRR4 CRB
 
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Ajay

Lifer
Jan 8, 2001
15,430
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Ian put this up on this Twitter page:

IceLake_BlockDiag.png

Looks like interconnected rings. Hopefully it's better than the Skylake mesh. Ian suggests that RLink may be for off chip optical connections. Too bad (for Intel) that we aren't looking at Sapphire Rapids.
 
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moinmoin

Diamond Member
Jun 1, 2017
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Ian put this up on this Twitter page:

View attachment 44683

Looks like interconnected rings. Hopefully it's better than the Skylake mesh. Ian suggests that RLink may be for off chip optical connections. Too bad (for Intel) that we aren't looking at Sapphire Rapids.
Skylake mesh was shown as "rings" as well though:

xcc28cores_575px.png


The difference is that in the tweeted image 1) the interconnects extend beyond the node to the border of the die and 2) there are additional interconnect "rings" at the top and right edge of it.

The big question is are those actual topology design changes worth mentioning beyond PR, or are these just changes to the visual presentation?
 

SAAA

Senior member
May 14, 2014
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This mesh ugliness just bothers me: I don't see any good in it and future solutions... thousands of elements wasting more power and area in interconnects than actual logic.
One day it will be clear if a few larger cores with extremely wide execution stage will be better, making all that interconnect moot by having all the data handled in one pool were it can be manipulated accordingly.
We have stalled with frequency and soon will with cores scaling, maybe in-memory computation will be a solution by then.
 

Bouowmx

Golden Member
Nov 13, 2016
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If I understand the current situation, Tiger Lake-U cannot be undervolted in software, but Tiger Lake-H can.

Also, the i7-11800H supports +400 MHz overclock.
11095783.JPG

I hope this tunability comes back to mobile platforms since they were taken away in recent times.
 
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jpiniero

Lifer
Oct 1, 2010
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I hope this tunability comes back to mobile platforms since they were taken away in recent times.

That was because of Plundervolt. Apparently the 11800H and 11900H have partial unlocking. As the post says enabling the unlock was necessary to be able to overclock/undervolt. Also they were able to set the Gear to 1 with 3200 memory.