@Edrick Pretty good chance we'll see one. I can't see why not. As to when it'll arrive, server parts are a priority, so maybe summer?
Icelake-X would be a waste of 10nm capacity, I don't think we will see this, it's unlikely.
@Edrick Pretty good chance we'll see one. I can't see why not. As to when it'll arrive, server parts are a priority, so maybe summer?
which is 160 cores, a crazy high, near outlandish number, and likely near impossible to wire to the I/O die successfully with even tech from two years down the road), which in a 2P system, is 24-28 compute dies, or 192-224 cores.
The simple math ignores a lot of reality, such as 5nm only giving a small benefit in terms of perf/watt, and power being the big limited of modern MPUs. Clock down might be big enough that its not worth all that effort. It's not just clock speeds that are at a glacial pace, but voltage scaling.
Also they might be able to get that many if they use the last generation Zen 3. With Zen 4, this is where it straddles the line of being unreasonable.
Wider cores follow the inverse square law, where power increase and number of transistors is roughly equal to square of the performance improvement - 2x perf gain, 4x area and power.
Where are you seeing that 5nm is only a minor improvement?
Remember 20nm? What about 10nm? 5nm is the same. It's slightly more than a half node when you consider how it was 20 years ago and what a full node really was.
I should have said small, but compared to what he's suggesting its "minor".
Definitely not. I'm not sure what gave you that impression, but 5nm is a full node improvement.
What makes you say that?Sure if you take the "new" standards its full node. But the transistor performance gain is actually same as from 16 to 10. Back then many skipped the 10nm and waited for 7nm. Same happened with 20nm.
Sure if you take the "new" standards its full node. But the transistor performance gain is actually same as from 16 to 10. Back then many skipped the 10nm and waited for 7nm. Same happened with 20nm.
20nm also sucked for other reasons. Like it was a hot mess. i had a 20nm chip in an old mobile. was hot, was messySure if you take the "new" standards its full node. But the transistor performance gain is actually same as from 16 to 10. Back then many skipped the 10nm and waited for 7nm. Same happened with 20nm.
Icelake-X would be a waste of 10nm capacity, I don't think we will see this, it's unlikely.
Icelake-X would be a waste of 10nm capacity, I don't think we will see this, it's unlikely.
It's also a non-trivial improvement in circuit density. If they choose to take all 30% of the power improvement AND they also move the 12nm I/O die to N7 or some other power improved node, then there will be enough total package power improvement headroom to accommodate 50% more CCDs while maintaining the current MHz targets. That's 96 cores per package, and, with SMT2, 384 threads in a 2P server, with wider cores and higher IPC than Rome.
That's going to be hard to keep up with, even with ~38 core XCC dies at 10nm+/SF.
How can you assume that you can have both 50% more cores AND wider and higher IPC SMT2 cores? How much more power are you assigning to each core in your calculation compared to Rome?
So both AMD and NVIDIA canceled their 20nm GPUs because Qualcomm designed a bad SoC? Come on...@itsmydamnation
That's is a flaw in the design from Qualcomm, not of the process node. Can we stop blaming foundries for bad designs from the companies ? Same thing now with people trashing SS for upcoming Nvidia's GPUs. Vega was a failure when jumping from 28nm to 14nm FinFet.
Isn't he talking about Genoa and not Milan? That seems not unrealistic for Genoa.
TSMC N5's xtor performance is like that of a half node, but at an ~85 decrease in area - that's more like a full node. That's why the 5N node will be used (plus the large reduction in masks/process steps).Remember 20nm? What about 10nm? 5nm is the same. It's slightly more than a half node when you consider how it was 20 years ago and what a full node really was.
I should have said small, but compared to what he's suggesting its "minor".
IMO all bad dies and the dies that can't clock high enoughHow many 10nm wafers are going to go towards Pentium production under the current circumstances?
IMO all bad dies and the dies that can't clock high enough