Discussion Intel current and future Lakes & Rapids thread

[ondma]

Such comments like this aren't funny anymore. If you think Icelake runs at 3.9 Ghz all the time you are deluded.

At the end of the day, that seems to me to be the biggest failure of 10nm; it doesnt appear to be any more power efficient than 14 nm. One could live with the lower clockspeeds in mobile if there was a good power savings that allowed running at sustained higher speeds, but it just doesnt seem to work out that way.

 

[naukkis]

At the end of the day, that seems to me to be the biggest failure of 10nm; it doesnt appear to be any more power efficient than 14 nm. One could live with the lower clockspeeds in mobile if there was a good power savings that allowed running at sustained higher speeds, but it just doesnt seem to work out that way.

Other parts of SOC seems to be fine expect cpu cores. If core need twice as many transistors to switch to operate it needs twice as efficient process to be at same efficiency level than it's smaller rival. Sunny Cove cores are ridiculously complex, they are totally different level than their rivals or Skylake. And they got only 18% IPC uplift from that complexity - those cores just suck.

 

[jpiniero]

At the end of the day, that seems to me to be the biggest failure of 10nm; it doesnt appear to be any more power efficient than 14 nm. One could live with the lower clockspeeds in mobile if there was a good power savings that allowed running at sustained higher speeds, but it just doesnt seem to work out that way.

It's a yield thing. They have to be binning as loose as possible so most chips that actually end up not having any defects end up as the 1065G7 and the remainder as the 1035G7. And so on and so forth. That's part of the reason the 1068G7 and the Icelake-Y models never got released (until now/soon)... they have been stocking up the 1% for them.

If yields improve you will see things get better in that front with Tiger/Alder.

 

[coercitiv]

Sunny Cove cores are ridiculously complex, they are totally different level than their rivals or Skylake. And they got only 18% IPC uplift from that complexity - those cores just suck.

I'm having a hard time believing Intel messed up both arch and process. As long as we know process is in a bad place, as long as we see major efficiency difference between ICL i7 and i5, we have little reason to believe the cores themselves are the problem.

 

[mikk]

You know what else is delusional? Expecting average clocks to increase considerably despite difficulties with increasing max single-core boost.

Are you stupid? You have to assume a) zero IPC increase for Willow Cove b) 4.3 Ghz ES Stepping B0 is a final clock speed which won't improve with C0 or D0 stepping c) Singlecore turbo specs reflects the real world performance under sustained load and multicore speed

You have no clue about a/b/c. The max singlecore turbo is one metric and pretty much irrelevant for real world usage. A much bigger importance is the multithread turbo and even bigger the sustained clock speed under a certain power budget because the multithread boost is a theoretical best case spec. Your comment is a laughable joke therefore.



Insults are not allowed.


esquared
Anandtech Forum Director

 

[John Carmack]

At the end of the day, that seems to me to be the biggest failure of 10nm; it doesnt appear to be any more power efficient than 14 nm. One could live with the lower clockspeeds in mobile if there was a good power savings that allowed running at sustained higher speeds, but it just doesnt seem to work out that way.

Wasn't there a rumor that Intel's first iteration of 10nm was more power hungry than their 22nm or am I imagining things?

 

[coercitiv]

Are you stupid?

Take a breather mate. I respect you and follow your posts with interest, but only as long as you hold it together, especially as things are likely to get a lot more tense for everybody in the next few months.

Everybody assumed TGL would bring a nice IPC increase until some benchmark leaks said otherwise. And that would have been fine honestly, there's so many unknowns with isolated benchmark runs that anything was still possible for Willow Cove, especially as that larger cache is bound to have positive effects in some workloads. But then Intel PR happened, or more exactly the lack of. Do you honestly expect Intel to sit around with a really good product in their hands and say almost nothing about it, just promise a vague "double-digit performance gains" after the hell they've been through with 10nm? If TGL-U was anything but mediocre they would have crashed AMDs Renoir party with all the bells and whistles.

If Willow Cove delivers in terms of healthy IPC and sustained clocks increase, I'll be happy to eat some crow. Won't be the first time, won't be the last.

https://twitter.com/x/status/1240669531313328128

 

[jpiniero]

Yeah I am pretty confident 2.7/4.3 is final clocks for the Tiger 28W model.

 

[dmens]

I'm having a hard time believing Intel messed up both arch and process.

What do they say on the internet?

Hold my beer.

 

[jpiniero]

1030ng7 - Geekbench 5 CPU Search - Geekbench

2020 MacBook Air review: No news is good news

[Author’s Note: I’ve updated this piece to change the chart at the conclusion of the story. I put the wrong numbers in the chart, and those numbers were wildly misleading about iPad Pro…

sixcolors.com

At least in Geekbench, the 2020 Air is a good deal faster in both single and multi compared to the 2018/2019 Air.

 

[IntelUser2000]

If core need twice as many transistors to switch to operate it needs twice as efficient process to be at same efficiency level than it's smaller rival. Sunny Cove cores are ridiculously complex, they are totally different level than their rivals or Skylake. And they got only 18% IPC uplift from that complexity - those cores just suck.

Let's not jump to conclusions shall we?

The transistor count has increased by 38%? 39%? That's exactly in line with the inverse square law, which in this case says performance increase is roughly equal to square root of the transistor count(thus power use). This is why we are in the multi-core era, so the curve is more linear. We no longer can increase power to increase ILP, especially true since gains from process are both hard to come by, and when it does, its much smaller than it used to be.

In the Icelake implementation of Sunny Cove cores, its almost exactly following the inverse square law.

I'm having a hard time believing Intel messed up both arch and process.

Me neither. I'm guessing its process, and while Icelake's 10nm is acceptable, it probably won't be until Tigerlake's 10nm+(or ++ doesn't matter) it gets to mostly what they want it to be. Their presentation about backporting also shows the Tigerlake's 10nm version to be one that's going to be used to backport, not Icelake's(and definitely not Cannonlake lol) because it'll be in a better condition.

In light of that I can believe average clocks improving significantly. I think it'll be a significant improvement(20-30% over Icelake as with leaks) and obsolete the 6 core Cometlake parts.

Typically companies including Intel opt for shouting from the rooftops when the product is really good, but that's not always the case.

Also the issue here is even if Tigerlake is 50-60% faster than Renoir in GPU and 20% faster in ST, it'll still be significantly behind in MT workloads because it has half the cores. So its not a clear win. The err in Intel's part is not having a 6 core Tigerlake-U part. That would have been a competent part in all areas.

Are you stupid?

Buddy, you might need to take a little more than a bit of a breather. You can like whatever you like, but if it gets in the way of being nice to people, then it'll be better for you giving it up.

Technologies are here supposedly to help us. If it results in calamity because of it, then we're better off without it. The moment we lose the real goals of advancement is when we should stop.

 

[naukkis]

The transistor count has increased by 38%? 39%? That's exactly in line with the inverse square law, which in this case says performance increase is roughly equal to square root of the transistor count(thus power use). This is why we are in the multi-core era, so the curve is more linear. We no longer can increase power to increase ILP, especially true since gains from process are both hard to come by, and when it does, its much smaller than it used to be.

Try instead like 3x. Sunny Cove is huge, 300 million transistor core as stated Keller. Skylake has something like 100 million core transistors. Sunny Cove core at 10nm is twice as big as Zen2 7nm, and they should have similar transistor densities. And they got only 18% average IPC improvement over Skylake. No wonder that those suck power. They probably need to abandon whole Cove-arch and try again to be competitive, as Zen3 will bring similar IPC-gains and pretty sure won't be twice as big as Zen2.

 

[coercitiv]

In light of that I can believe average clocks improving significantly. I think it'll be a significant improvement(20-30% over Icelake as with leaks) and obsolete the 6 core Cometlake parts.

At this point all I want to see from Intel is a new gen product that beats CML-U across the charts: ST, MT, efficiency. It's their second* working iteration of 10nm, second* working iteration of Cove arch, it needs to beat grandpa Skylake hands-down.

*we'll just pretend Palm Cove and the early 10nm- never happened.

 

[OriAr]

Try instead like 3x. Sunny Cove is huge, 300 million transistor core as stated Keller. Skylake has something like 100 million core transistors. Sunny Cove core at 10nm is twice as big as Zen2 7nm, and they should have similar transistor densities. And they got only 18% average IPC improvement over Skylake. No wonder that those suck power. They probably need to abandon whole Cove-arch and try again to be competitive, as Zen3 will bring similar IPC-gains and pretty sure won't be twice as big as Zen2.

Coffee Lake has 217 million transistors per core, while Ice Lake has 300 million. 300/217 = 1.38 > ICL has 38% more transistors per core in it than CFL.
For comparison, Zen 2 has 4 billion transistors per CCD so roughly around 350-400 million transistors per core, not that much of a difference between this and ICL.
Zen 1 has around 220 million transistors per core, again, not a big difference between AMD and Intel here.
Both companies are largely contained by physics after all.

 

[naukkis]

Coffee Lake has 217 million transistors per core, while Ice Lake has 300 million. 300/217 = 1.38 > ICL has 38% more transistors per core in it than CFL.
For comparison, Zen 2 has 4 billion transistors per CCD so roughly around 350-400 million transistors per core, not that much of a difference between this and ICL.
Zen 1 has around 220 million transistors per core, again, not a big difference between AMD and Intel here.
Both companies are largely contained by physics after all.

Core transistor increase won't look so massive if all caches and interconnect is also included. Last twenty years cpu's OOO-window has been hovering between 100 and 200 instructions, only Skylake and Zen2 went to bit over(224) Sunny cove increases that to 352 and Keller talks that next generations increase that to 800(with core transistor count increase of 50x). To keep up so many in-flight instructions make cores massive, that shows up when looking how big Sunny Cove is, it's easily twice the size of Zen2, which itself is twice the size of N1(128 instruction OOO-window).

Others want to kept that in-flight instruction window small to keep core efficiency and size in control. Intel instead went to have 18% IPC increase from over 50% increase in OOO-window, which isn't a great scaling at all.

Maybe Intel is on right track but I don't see it, and results so far ain't either.

 

[mikk]

Yeah I am pretty confident 2.7/4.3 is final clocks for the Tiger 28W model.

Are you confident the current 2.8 Ghz base clock 3dmark entries were false?

 

[RetroZombie]

Intel with this new tigerlake and icelake created a new problem they didn't had in the past, the cpus that weren't good enough for mobile would end up into the desktop line. They can only bin them to meet the mobile space requirements.

The other problem with their cpus is the tdp, they range from lie up to big lie.

 

[coercitiv]

Intel with this new tigerlake and icelake created a new problem they didn't had in the past, the cpus that weren't good enough for mobile would end up into the desktop line. They can only bin them to meet the mobile space requirements.

That was not true for their ultra-mobile lineup. These chips are built solely for mobile, and the U type SKUs have existed for a long time now.

 

[RetroZombie]

That was not true for their ultra-mobile lineup. These chips are built solely for mobile, and the U type SKUs have existed for a long time now.

Wasn't intel mobile line just desktop i3 cpus recently?

And 28W tdp doesn't look too ultra-mobile to me.
Qualcomm, apple and others will eat those at lunch.

 

[witeken]

4.3/3.9=1.10

“Double-digit performance gains”. This isn't funny anymore.

Intel said it would be much more than 10%.

 

[lobz]

Other parts of SOC seems to be fine expect cpu cores. If core need twice as many transistors to switch to operate it needs twice as efficient process to be at same efficiency level than it's smaller rival. Sunny Cove cores are ridiculously complex, they are totally different level than their rivals or Skylake. And they got only 18% IPC uplift from that complexity - those cores just suck.

... and I'm telling you, that neither willow or golden coves will be any less ridiculously complex. Let's see what they can do with 7nm - some time in the distant future.

 

[lobz]

Intel said it would be much more than 10%.

It's also OnTrack™, right?

 

[jpiniero]

Intel said it would be much more than 10%.

At 2.7, that would be a 18% increase in base clock over the 1068G7.

 

[RetroZombie]

Maybe Intel is on right track but I don't see it, and results so far ain't either.

What is even worst wih all that is the cpu core getting bigger and bigger and without increasing the number of cpu cores.
Where intel does only 4 cpu cores some mobile arm company will do 16. It wont be funny any more.

If all those arm companies doing those recent arm server chips does some mobile chip for laptops it will be game over for intel.

 

[uzzi38]

Are you confident the current 2.8 Ghz base clock 3dmark entries were false?

For the most part I agree in thinking the 2.7GHz base isn't final clocks, but looking at 2.8GHz base clock benchmark samples is not the way to prove that.

Lets not forget there are Ice Lake ESs in benchmarks with a 2.4GHz base, shall we? Despite the fact that there are no final chips with a 2.4GHz base clock.

https://twitter.com/x/status/1240691825838419969

Look elsewhere in that thread and you find D0cTB who explains why this is the case. Final clocks aren't based off the few chips that could. Final clocks are done taking the full spectrum of chips into account. Where ESs reflect the clocks of a certain chip in question, and Intel releases ESs based upon how they expect the chips to release in the future, that doesn't mean they will.

Intel can overestimate the future of their own process, and in the case of Ice Lake ESs, did exactly that. They overestimated, which is why we now have benchmarks using ESs with higher base clocks then what was ever released.