I should add that if Tigerlake is using chiplets, they would have an incentive to not hold it back if it's ready because of the better yield they would get.
Tiger Lake, at least as far as client parts are concerned, is the follow on to Ice Lake and is U/Y only. It's a monolithic, 10nm 4+2 die with 4 Willow Cove cores, GT2 Gen12/Xe graphics with up to 96 EUs, and integrated Thunderbolt 3/USB4. It's an ~150 mm^2 die all-in, and trying to break it into smaller pieces would pose way more challenges than could possibly be warranted.
If Tigerlake is not monolithic, then cutting the iGPU in half won't help them. I strongly suspect that, in light of Intel's yield problems on 10nm, Tigerlake will use EMIB to connect CPU and SoC die/iGPU in order to reduce die sizes and improve yields. It may just be that they can't reliably produce dice larger than 4c on 10nm in any significant quantity (see delays for Icelake-SP).
Rocketlake is a different issue altogether. Willow Cove implemented on 14nm++(+) as Rocket Lake would be an interesting product. Perhaps too little/too late given that it'll be a 2020 product, but still a step up from Coffeelake/Comet Lake.
There is no possible universe where TGL-U/Y are not monolithic, it simply makes zero sense financially and technically for Intel to do otherwise. There are already engineering samples of 38C 10nm ICL-SP XCC dies back from the fabs, no? (Not that they'll actually be able to yield well enough to make a profitable or even competitive product, but at least Intel wants everyone to know that they're attempting this.)
The only client chips we've seen on leaked roadmaps that even hinted at a multi-chip module strategy are Rocket Lake-U, which is the follow on to Comet Lake-U. RKL-U is a monolithic, 14nm 6+1 die with 6 Willow Cove cores and GT1 Gen12/Xe graphics with up to 32 EUs. It will be available in 4 and 6-core flavors with GT0 (no integrated graphics), GT0.5 (16 EUs), or GT1 (32 EUs). Implementing the full 96 EU GT2 Gen12 configuration from TGL isn't practical at 14nm, so RKL is GT1 only, but for customers who are willing to pay more for graphics, it looks like Intel is planning MCMs with a discrete Xe GPU called "DG1". This is a Gen12 LP part and probably a 10nm die with a very similar layout to TGL GT2. The TGL-U CPU die is rumored to have a direct PCIe 4.0 x4 connection—sort of a U-series version of PEG lanes. I reckon that RKL-U will have the same, and the DG1 die will be connected to the CPU via a PCIe 4.0 x4 link using standard substrate traces, but it will also include an HBM2 stack connected to the DG1 die via EMIB (Kaby Lake-G style). Mind you, Intel has no problem yielding massive parts on 14nm at this point, but if they make them too big, either nobody is going to be willing to pay for them and Intel will take a beating on margin, and/or they will continue to run into 14nm capacity issues.
Rocket Lake will also have H and S series parts, and it looks like 6+1 and 10+1 monolithic 14nm dies are planned. This will yield SKUs with 2, 4, 6, 8, and 10 cores with GT0 (no integrated graphics), GT0.5 (16 EUs), or GT1 (32 EUs) UHD Graphics. I'm guessing the "DG2" discrete GPU which is Gen12 HP with 128, 256, or 512 EUs is an option for pairing with an H die to create a Kaby Lake-G style MCM.
Yes but the scores on this site are really good so early in development, it beats the best i7-8565U devices on userbenchmark. The ES samples from Icelake 1 year before launch were much slower clocked, look at this from 11 months ago:
https://www.userbenchmark.com/UserRun/10940550
10nm is clearly in much better shape now. I still wonder if Tigerlake is made on 10nm++ or really on 10nm+ as Intel claimed.
I think Intel is attempting to take a mulligan for their Cannon Lake / Palm Cove / Gen10 misadventure with 10nm and start over again. That makes Ice Lake 10nm and Tiger Lake 10nm+. They also attempted to shift journos to the less specific "14nm class" and "10nm class" terminology, because simply adding a plus every time they tweaked a process was clearly not forward thinking enough. But it would be interesting to know how they refer to the process internally, i.e. whether TGL is 1274.7, 1274.12, or some other version entirely.