AMD not using super expensive packaging methods for their interconnects, such as using giant interposers, at least for their EPYC CPUs, certainly helps it seems. I also suspect the economics of packaging a bunch of chiplets place an effective cap at how many chiplets AMD can add before they are forced to start increasing the amount of cores on each chiplet (beyond also power and engineering limitations I mean) but I don't think they are approaching that crossroad with zen 4 genoa quite yet.I think the subject of "optimal" chiplet sizes deserves a bit more nuance. A larger chiplet size decreases yields, yes, but it also means less interconnect overhead (in both area and power) and a larger L3 domain (particularly useful for VM bucketing). AMD's solution is empirically successful, but I don't think it's necessarily the only viable path. And obviously that equilibrium is heavily dependent on what packaging tech is available.
But I agree with IntelUser2000 here in that the specifics of their chiplet implementation isn't Intel's main problem right now. Sure, it weighs on their financials, but if they end up PnP competitive with AMD, they can at least get decent revenue. And obviously, since Intel also fabs them, their effective wafer prices should be substantially cheaper than AMD sees. Though with their talk of an "internal foundry model", that tradeoff might change somewhat.