Then there is Cannonlake 2 + 0, I am assuming this is a CPU only instead of having GPU silicon disabled. How is it for ?
It's for Shareholder PR so they can say they are still ahead of the foundries. They are selling test chips essentially.
Then there is Cannonlake 2 + 0, I am assuming this is a CPU only instead of having GPU silicon disabled. How is it for ?
So the reason Skylake-X and SP cores are so large isn't just because of 1MB L2 and AVX-512. AVX-512 in terms of added area is actually relatively small.
There's also the CHA(Caching Home Agent), Snoop Filter, power management, and logic needed for the mesh. I would say about half of the new space is taken up by them. In Broadwell EP chips, the CHA and Snoop filter functions were spread elsewhere, so the cores looked similar in size to consumer Broadwell ones. With Skylake, each cores have CHA and Snoop Filters.
They are actually critical for server chips. But they aren't necessary for HEDT. The HEDT market is way too small to justify a dedicated core development though.
CHA is much larger than I would have imagined and AVX512 is much smaller than I was led on to believe by others.
They are actually critical for server chips. But they aren't necessary for HEDT. The HEDT market is way too small to justify a dedicated core development though.
I also got it from PCWatch.
Intel could split the line into three, by going Mobile, Desktop(including HEDT) and Server.
I wonder if they can opt to go traditional MCP, or even EMIB. Rather than basing HEDT off servers that brings added memory latency, die complexity, and cost increases they can put multiple of the top Desktop die. Say if top HEDT was two 8700K dies in one package connected by EMIB. It would be just like how AMD is doing it with Threadripper. You'd lose some frequency, but have 2x the cores, 2x memory channels, and 2x PCIe lanes.
The HEDT market is too small to justify dedicated core development, but the overall desktop computer market is not.
No, what Intel needs to do is to split the die into different subsystems and to serve the different markets, they would build SoCs with the appropriate building blocks. For a DT part they would exclude a GPU/media tile, LTE modem tie, etc.
Sometime this year, and maybe.When are the new Intel CPU's and Z390 motherboards due to release again? We are expecting 8c/16t this time around correct??
LOL , OK first half or second half?? or is it a toss up right now??Sometime this year, and maybe.
Supposed to be 1H18 for Z390, and 8 cores seems very vaporish at this time...LOL , OK first half or second half?? or is it a toss up right now??
The low power, lost cost, and integrated Notebook and Desktop parts benefit tremendously from having a monolithic design over EMIB/MCM. The die sizes are small so there's no cost advantages.
Supposed to be 1H18 for Z390, and 8 cores seems very vaporish at this time...
70-110 mm2 isn't small. Not anymore.
"supposed to be" means it will not be, of course.1H18 for the mainstream 300 series chipsets. Likely Q3 for Z390.
https://wccftech.com/intel-coffee-lake-300-series-z370-z390-chipset-leak/
They aren't going to release Z390 in Q1 when Z370 has been launched less than 6 months ago.
Sure it is. Packaging costs dominate at that die size.
"supposed to be" means it will not be, of course.
Q1 is not the same as 1H.
wccftech is generally not a reliable source.
Intel will release when Intel releases.
https://www.tweaktown.com/news/59851/intels-next-gen-z390-ready-coffee-lake-1h-2018/index.html
Intel's next-gen Z390: ready for Coffee Lake-S in 1H 2018
Given the footnote and Intel's situation, I think we will see Z390 right at the end of 1H18.
Some time within the previous week, processors got ahead of the motherboards: https://videocardz.com/75095/new-coffee-lake-cpus-already-in-stock-and-shipping
70-110 mm2 isn't small. Not anymore. Unless Intel intends to go smaller than that, client dies using EMIB makes sense. It may only be PCH <-> CPU <-> GPU but that would be good enough.
It's very small. AMD's APU is twice that size.