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Discussion Intel current and future Lakes & Rapids thread

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TESKATLIPOKA

Senior member
May 1, 2020
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Zen 3 increased core size only by 14% over Zen 2. Sunny Cove is how much larger than Skylake? 50%? Willow Cove adds cache but the reason for the addition seems mysterious as it performs pretty much like Sunny Cove.
Precisely. Intel core even at 10nm is a lot bigger than AMD's while performing comparably at best.
Now the question is how much bigger Colden Cove cores will be compared to Willow Cove.
I am very interested in new info about Alder Lake at HotChips 33, but considering It's only 30min I don't expect much being revealed.
 

DrMrLordX

Lifer
Apr 27, 2000
17,865
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I think it is almost certain Intel will use TSMC 3nm also.
Rumour was that TSMC didn't want to do anything long-term for Intel. They may supply Intel with some 6nm and (eventually) 5nm wafers, but that's about it. In the long term, it's in TSMC's best interest to eliminate Intel as a rival. None of TSMC's other customers have ever competed with TSMC directly as has Intel.
 
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eek2121

Golden Member
Aug 2, 2005
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Alder Lake-P 14 core ES spotted on Geekbench:

 

jpiniero

Lifer
Oct 1, 2010
10,129
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Alder Lake-P 14 core ES spotted on Geekbench:

They need to fix the detection.
 

TransientStudent

Junior Member
Aug 16, 2020
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Rumour was that TSMC didn't want to do anything long-term for Intel. They may supply Intel with some 6nm and (eventually) 5nm wafers, but that's about it. In the long term, it's in TSMC's best interest to eliminate Intel as a rival. None of TSMC's other customers have ever competed with TSMC directly as has Intel.
Well, Intel is a large TSMC customer today, and the DG2 graphics stuff is on TSMC 6nm as far as I know.

Nobody can predict the future, but a very plausible scenario is that Intel starts to make tiles at TSMC, and combine them with some tiles they produce themselves. Sort of like AMD using TSMC for the advanced nodes, and GF for some 14/12. Intel will then play the part of GF, and do the packaging themselves.

Then at some point Intel might spin of the foundries. There are after all a lot of stuff not needing the absolute leading edge.

Will that plan be successful? Maybe not, but betting everything on Intel's own manufacturing is certainly more dangerous. And if this is the actual plan, then it makes sense that Intel is not a heavy buyer of EUV equipment.
 
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Gideon

Golden Member
Nov 27, 2007
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Sunny Cove is how much larger than Skylake? 50%?
It looks like 37%
Alright, a first look analysis. Cypress Cove is ~37% larger than Skylake Client under the "same" 14nm process. The FPU got surprisingly large (+~45% vs SKL C), even though it has just one 512b "unit" (2x256b port fusion), it's close in size to the SKL Server FPU (2x256b + 512b).
The FPU being 50% larger seems particularily strange, as It's not larger (as Skylake Server is) just fused.
 

JoeRambo

Golden Member
Jun 13, 2013
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The FPU being 50% larger seems particularily strange, as It's not larger (as Skylake Server is) just fused.
Not really strange to me, Skylake Server has full 512bit vector FMA on port5, Ice Lake still has wide 512bit vector ALU/Shuffle unit on Port5. Size of FP PRF has also grown in IceLake. End result of this backport on 14nm is 50% more FPU area compared to Skylake client.
The decision to drop FMA on port5 in client Icelake was probably driven more by power, than by area, they saved maybe 5% area max.
 
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IntelUser2000

Elite Member
Oct 14, 2003
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It looks like 37%
Thanks.

37% area growth for 18% performance improvement is not bad, because that's naturally in line with the square root law.

But if you take the same figure and realize that the competitor is already advantaged in terms of die area/performance, then it's bad. Zen 3 is 4mm2 while Sunny Cove is 6.9mm2. Even if Sunny Cove didn't grow at all in area over Skylake, we're still looking at performance/area disadvantage that's significant compared to Zen 3.
 
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Zucker2k

Golden Member
Feb 15, 2006
1,532
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There is no need to discuss the sense, or rather complete nonsense, of such a cooling solution here, it is just the way it is. The de facto doubling of the combined power consumption of CPU and cooler is simply impractical and the exact opposite of efficient working. The above drawing shows the areas in question and also the recommendation for an airtight cover. The picture below shows how something like this looks in practice with the Cooler Master MasterLiquid ML360 Sub-Zero.
Intel may need to create a 'Common Sense' department under their Research & Development division to check some of these resource-wasting garbage they keep throwing in enthusiasts' direction.

 
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coercitiv

Diamond Member
Jan 24, 2014
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ADL-S looks like it will will bring about lots of changes: switch to DDR5 or blend of DDR4/DDR5 at launch, switch to ATX 12VO as new standard for motherboards and PSUs, and now this weird Peltier element leak. (that is hopefully just an uninspired marketing tactic)

At best this will confuse the heck out of any regular Joe looking to build a next gen computer. Only Rambo Joes will make it.
 

Dave2150

Senior member
Jan 20, 2015
638
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Rumour was that TSMC didn't want to do anything long-term for Intel. They may supply Intel with some 6nm and (eventually) 5nm wafers, but that's about it. In the long term, it's in TSMC's best interest to eliminate Intel as a rival. None of TSMC's other customers have ever competed with TSMC directly as has Intel.
Intel will take full advantage of TSMC's best processes, even if they have to outbid AMD, as this is a very good way to cripple AMD long term and send them back to Bulldozer era.
 

uzzi38

Golden Member
Oct 16, 2019
1,817
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Intel will take full advantage of TSMC's best processes, even if they have to outbid AMD, as this is a very good way to cripple AMD long term and send them back to Bulldozer era.
Intel will take advantage of TSMCs nodes for various different products, but their actions have no consequence on AMD's ability to procure leading edge node wafer capacity is minimal at best.
 
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