Discussion Intel current and future Lakes & Rapids thread

[LightningZ71]

Following the previous post, this is also why it is difficult to get apples to apples comparisons between desktop first processors and mobile first processors. Just using the Apple M1 as an example, Apple used a set of optimizations for that chip that were targeted around two fundamental facts: it wasn't going to clock higher than just above 3Ghz and they were going to use a lot of fixed function units, such as the NPU, instead of trying to do everything on the CPU core. This allows the function units to use the best transistor strategy for their purpose and then be turned off. This leads to lower idle power, and lower power used overall because the chip will love in the lower half of the power/frequency curve. This can significantly amplify the benefits of choosing ARM as the ISA. Node density also gives a benefit because it gives you the transistor budget to actually manage to fit all of those fixed function units on a processor. In other words, being stuck on a larger node, you don't get the advantage of those units, their function has to be emulated on the CPU at more cycles that the fixed function unit would need with transistor usage strategies that aren't targeted at their ideal usage.

 

[dmens]

You are completely ignorant, clueless, trolling or just stupid on this topic. Once again, there is a window of several weeks if the projected production schedule is 6-12 months away. This is not a secret, these roadmaps had been leaked in the past. They have a rough estimate and most likely could narrow it down to 1-2 months but the thing is they do not share these more exact schedules to the public for several reasons. Second half, first half, end of the year, holiday seasons etc. are typically public announcements without sharing too much. Your chronic drama style looks foolish.

LOL, still with the roadmaps? You are literally a dabbler eating table scraps and pretending to know how it is cooked. How embarrassing.

 

[Asterox]

If this turns out to be correct, or ddr5 is still to expensive for averege users.

For example, Alder Lake socket 1700+cheep motherboard +ddr4 minimum 100$.Motherboards with ddr5 suport, price is hm for example minimum 200-250$.

 

[JoeRambo]

Lol @ 4800CL40. Welcome our new 16.66ns first word latency overlords.

Anyone with B-Die kit of 16-32gb will happily pass over this memory that is twice as slow as decent 3600CL15 kit. But time, memory vendors and voltage will sort things our and ~6400CL28 will start to get fun again. Hopefully at that point Intel will have at least 12 fat cores that would need that much bw in first place.

 

[jpiniero]

That would be kind of dumb if the big pin count increase is due to DDR5 and it doesn't end up actually getting used much. Hadn't thought about the impact of increasing the pin count on how much that would change board prices.

 

[Exist50]

DDR5 offers substantial benefits beyond the nominal MT/s increase. Would be quite a shame if it's not widely available.

 

[mikk]

LOL, still with the roadmaps? You are literally a dabbler eating table scraps and pretending to know how it is cooked. How embarrassing.

I can tell you for sure you are right now the most embarassing user in this thread. You were wrong and are unable to accept your roadmap babble, your postings are full of stupidity and full of troll biased stuff, it should be clear by now for everyone you hate Intel but the most annoying is your stupidity and low level trolling, your posting history is telling. I mean you have no real arguments and are clearly someone with zero knowledge and pretend to be an expert which is embarrassing.

 

[DrMrLordX]

@Asterox

If Alder Lake-S is truly going to launch in Q3 2021, why frame it as H2 2021 to the public? Usually you use an H1 or H2 designation to hide something - make someone think it's going to be Q1 or Q3 when in reality it's Q2 or Q4.

 

[mikk]

@Asterox

If Alder Lake-S is truly going to launch in Q3 2021, why frame it as H2 2021 to the public? Usually you use an H1 or H2 designation to hide something - make someone think it's going to be Q1 or Q3 when in reality it's Q2 or Q4.

Because nothing is safe, it might come in September but might also come in October or even later if something goes wrong. And even Intel can't know it for sure 3 quarters in advance. Look to RKL-S, it was supposed to come in January and slipped into March. I think Tigerlake-U also was anticipated a bit earlier. If they announce September everyone screams delay when it doesn't come, they usually avoid exact schedules for this reason (among other reasons). Otherwise they could easily share their confidential roadmaps, this is not how it works in this industry. I doubt we will get a more precise answer from Intel before Computex.

 

[jpiniero]

If Alder Lake-S is truly going to launch in Q3 2021, why frame it as H2 2021 to the public? Usually you use an H1 or H2 designation to hide something - make someone think it's going to be Q1 or Q3 when in reality it's Q2 or Q4.

It wasn't just S, it was S and P.

 

[DrMrLordX]

Because nothing is safe

Safe compared to what? Intel has a long history of paper launches with low availability on any number of parts (including halo parts). 9900K availability took maybe a month, KS availability was never good, and 10900K also took about a month before you could reliably buy one (though buy pressure for that chip was a lot lower than the 9900K). If Intel already has the tapeout and they're already starting to cut dice, then it's just a matter of binning and stockpiling enough for their launch.

The only possible "unsafe" factor here is the question of whether or not Intel can get enough Alder Lake dice to yield off their 10SF/10SFE wafers to meet launch targets on an acceptable cost basis.

It wasn't just S, it was S and P.

I thought S was first and P would be later? Have they pushed S back into the P launch window?

 

[jpiniero]

I thought S was first and P would be later? Have they pushed S back into the P launch window?

The quote in question said basically they would start manufacturing S and P in 2H. They could start P in December for a release in April/May for all we know.

 

[Asterox]

@Asterox

If Alder Lake-S is truly going to launch in Q3 2021, why frame it as H2 2021 to the public? Usually you use an H1 or H2 designation to hide something - make someone think it's going to be Q1 or Q3 when in reality it's Q2 or Q4.

Hm, yields on 10nm it's not even close to yields on 14nm with battalion of +.Intel is simply not sure of the exact course of events.

As goes to Alder Lake Big Little CPU configuration on Desktop= i smell smoke in windows and various applications.Intel had no other choice, because I can't produce(to expensive+yields are blah) 16/32 CPU on 10nm with all Big 16 cores.Amd from first Ryzen CPU chose the optimal design. But "sleepy Intel" had no other choice, here we go Big Little or shot in the fog.

 

[jpiniero]

Hm, yields on 10nm it's not even close to yields on 14nm with battalion of +.Intel is simply not sure of the exact course of events.

As goes to Alder Lake Big Little CPU configuration on Desktop= i smell smoke in windows and various applications.Intel had no other choice, because I can't produce(to expensive+yields are blah) 16/32 CPU on 10nm with all Big 16 cores.Amd from first Ryzen CPU chose the optimal design. But "sleepy Intel" had no other choice, here we go Big Little or shot in the fog.

Intel's probally not going more than "10" as long as they use the ring anyway.

 

[LightningZ71]

I wonder if they will bring their mesh setup to lower end products that aren't in their X series? The ring seems to work well up to eight cores. Maybe keep it for lower core count, small dies and go to a mesh for the larger ones. They already use two different size dies for the 10 series, and in the 11 series, they will be two different architectures.

 

[eek2121]

Because nothing is safe, it might come in September but might also come in October or even later if something goes wrong. And even Intel can't know it for sure 3 quarters in advance. Look to RKL-S, it was supposed to come in January and slipped into March. I think Tigerlake-U also was anticipated a bit earlier. If they announce September everyone screams delay when it doesn't come, they usually avoid exact schedules for this reason (among other reasons). Otherwise they could easily share their confidential roadmaps, this is not how it works in this industry. I doubt we will get a more precise answer from Intel before Computex.

RKL-S was NEVER slated for January FYI. Internal roadmaps at Intel have always pointed at a March release date. The January date was a rumor that probably appeared due to CES and hype.

EDIT: Also, Ramping up Production != launch.

 

[coercitiv]

Maybe keep it for lower core count, small dies and go to a mesh for the larger ones. They already use two different size dies for the 10 series, and in the 11 series, they will be two different architectures.

What you're describing sounds a lot like what they already have in place with HEDT, if it were functional anyway.

 

[jpiniero]

I wonder if they will bring their mesh setup to lower end products that aren't in their X series? The ring seems to work well up to eight cores. Maybe keep it for lower core count, small dies and go to a mesh for the larger ones. They already use two different size dies for the 10 series, and in the 11 series, they will be two different architectures.

Desktop has been two die sizes for some time now. The 11th Gen smaller die is just a rebrand.

 

[Ajay]

Intel's probally not going more than "10" as long as they use the ring anyway.

I'd expect a hard limit of 12 cores, as with older Xeons. Going higher than that and rings of rings are needed - which doesn't work any better than mesh hence the design changes made in latter Xeons.
I have no idea what Intel is going to do with it 8+8 implementation.

 

[jpiniero]

I'd expect a hard limit of 12 cores, as with older Xeons. Going higher than that and rings of rings are needed - which doesn't work any better than mesh hence the design changes made in latter Xeons.
I have no idea what Intel is going to do with it 8+8 implementation.

On the small cores the stop is per cluster, so you have two stops. The IGP takes one presumably. That's 11.

 

[DrMrLordX]

I wonder if they will bring their mesh setup to lower end products that aren't in their X series? The ring seems to work well up to eight cores. Maybe keep it for lower core count, small dies and go to a mesh for the larger ones. They already use two different size dies for the 10 series, and in the 11 series, they will be two different architectures.

Well there's always . . .

I'd expect a hard limit of 12 cores, as with older Xeons. Going higher than that and rings of rings are needed - which doesn't work any better than mesh hence the design changes made in latter Xeons.
I have no idea what Intel is going to do with it 8+8 implementation.

Ring-of-rings might work better for workloads that could stay isolated to one ring - e.g. half the cores of the CPU or less. As long as your intercore communication isn't going out to the larger ring, you don't get enhanced latency. With mesh, you get higher latency no matter what you do. But it was topographically less-cumbersome and worked better when all of your cores were committed to something.

 

[JoeRambo]

During the last week Intel 10th gen CPUs are dropping in price at least in some places in Europe. For example 10700F is now 265EUR, 10600KF is 200EUR and so on.
Real welcome adjustment to reality of performance versus AMD and probably attempt to move product before 11th generation comes out.

Thanks AMD! Was looking forward to a day where 6C from AMD is same priced as 10C from Intel ( both without GPU ).

 

[Asterox]

During the last week Intel 10th gen CPUs are dropping in price at least in some places in Europe. For example 10700F is now 265EUR, 10600KF is 200EUR and so on.
Real welcome adjustment to reality of performance versus AMD and probably attempt to move product before 11th generation comes out.

Thanks AMD! Was looking forward to a day where 6C from AMD is same priced as 10C from Intel ( both without GPU ).

Yes is some places, but with 10600KF there is no CPU cooler."Old R5 3600 is bit cheeper+CPU cooler in the box".This is Mindfactory/Germany vs Geizhals/Austria short comparison.

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geizhals.at

If you look at sales numbers for various i5 10600 models, it looks absurdly vs R5 3600 small 114 000 CPU sold.

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[DrMrLordX]

During the last week Intel 10th gen CPUs are dropping in price at least in some places in Europe. For example 10700F is now 265EUR, 10600KF is 200EUR and so on.
Real welcome adjustment to reality of performance versus AMD and probably attempt to move product before 11th generation comes out.

Thanks AMD! Was looking forward to a day where 6C from AMD is same priced as 10C from Intel ( both without GPU ).

Even prices on the 10900k in the US are seeing a little downward pressure. The prevailing price is around $515, down from $540 where it had been for awhile.

 

[Gideon]

Some very early geekbench leaks of Alder Lake. It seems that the top mobile version will have 6 big and 8 small cores:

Intel Alder Lake-P mobile CPU with 14 cores and 20 threads spotted - VideoCardz.com

Intel Alder Lake-P makes a debut with 14 cores A new Intel 12th Gen Core CPU has been spotted on Geekbench. Intel Alder Lake-P CPU with 14-core with 20 threads has made its first appearance on Geekbench. This unusual configuration can be traced back to Intel’s Hybrid Technology, which utilizes...

videocardz.com

Unfortunately no performance numbers yet.