Intel's x86 decoders are always 1 complex and 3-4 simple.
Nehalem got x86-64 micro / macrofusion support since Conroe only x86-32.
Returning to the topic of the cache type, Intel cores are probably inclusive from the beginning and only Skylake-X and WillowCove introduced the non-inclusive type. Correct me if I'm wrong.
Nehalem got x86-64 micro / macrofusion support since Conroe only x86-32.
Returning to the topic of the cache type, Intel cores are probably inclusive from the beginning and only Skylake-X and WillowCove introduced the non-inclusive type. Correct me if I'm wrong.
Even this device scores 5107 points in Firestrike which is a lot better, did you check the JZWSVIC posting? He says DDR4 3200 2R x8 can reach 5100 in Firestrike. DDR4 3200 1R x8 is slower but can reach 4700 points and by far the slowest is DDR4 3200 1R x16, he says there is a 30% deficit to LPDDR4X 4266 2R*32 versus 1Rx16 on 1165G7. I'm sure the slow GPU scores are memory related and I guess the Vivobook 15 uses the slowest 3200 variant single Rank x16. edit: there is an even slower option I forgot: DDR4 3200 1RX16+1RX8
google translator:
It seems odd to me that there's so much back and forth regarding the release schedule of RKL-S when it was on roadmaps dating back to early 2018 as a Q1'21 launch. Are people just surprised that Intel confirmed it really is going to launch RKL-S in Q1'21 after all? I suppose it's not totally unreasonable to have lost faith in Intel's ability to launch anything new on time, even a backport to 14nm...
Same for ICL-SP. That was on Intel's June 2018 HPC roadmap as Q2'20 PRQ, H2'20 volume ramp. Intel confirmed during their recent earnings call that ICL-SP PRQ was underway during Q3'20 and volume ramp would take place in Q1'21. That's only one or two quarters behind their schedule from over 2 years ago for a product that we all knew was going to be a major ask of their 10nm manufacturing capabilities. ICL-SP was also shown in the 2018 roadmaps as only having a brief production window (3 to 4 quarters), so it's not terribly surprising that it won't have a particularly long market window. AFAIK, Sapphire Rapids isn't even in PRQ yet, so it should have at least some useful life, plus Intel has to figure out how to make big dies on 10nm at some point.
I also wanted to point out that once Intel committed to a dual-process roadmap, they're really stuck there until it makes economic sense to convert the bulk of their 14nm capacity to 10nm. They can't go all-in on TGL, RKL, ADL or whatever else because no matter which one you pick, the fabs will be capacity constrained and locked into a particular production schedule. They just have to ride it out as best they can until they have enough confidence to finally leave 14nm in the rearview.
And finally, now that DG1 has been formally unveiled, I wanted to point out that RKL was clearly *never* a chiplet design. It was a conventional monolithic die (including GT1 IGP) that could be paired with the DG1 companion die, which was a conventional PCIe Gen4 x4 dGPU based on Gen12/Xe-LP GT2. I assumed that they would at least be on the same package, and that would require using HBM2 as well. I should have realized that even that was too ambitious for a potentially high-volume product. DG1 simply has it's own LPDDR4X memory interface, which makes way more sense. That way they're free to do an MCP with a bog-standard substrate, or with separate packages as they did with Iris Xe MAX.
Same for ICL-SP. That was on Intel's June 2018 HPC roadmap as Q2'20 PRQ, H2'20 volume ramp. Intel confirmed during their recent earnings call that ICL-SP PRQ was underway during Q3'20 and volume ramp would take place in Q1'21. That's only one or two quarters behind their schedule from over 2 years ago for a product that we all knew was going to be a major ask of their 10nm manufacturing capabilities. ICL-SP was also shown in the 2018 roadmaps as only having a brief production window (3 to 4 quarters), so it's not terribly surprising that it won't have a particularly long market window. AFAIK, Sapphire Rapids isn't even in PRQ yet, so it should have at least some useful life, plus Intel has to figure out how to make big dies on 10nm at some point.
I also wanted to point out that once Intel committed to a dual-process roadmap, they're really stuck there until it makes economic sense to convert the bulk of their 14nm capacity to 10nm. They can't go all-in on TGL, RKL, ADL or whatever else because no matter which one you pick, the fabs will be capacity constrained and locked into a particular production schedule. They just have to ride it out as best they can until they have enough confidence to finally leave 14nm in the rearview.
And finally, now that DG1 has been formally unveiled, I wanted to point out that RKL was clearly *never* a chiplet design. It was a conventional monolithic die (including GT1 IGP) that could be paired with the DG1 companion die, which was a conventional PCIe Gen4 x4 dGPU based on Gen12/Xe-LP GT2. I assumed that they would at least be on the same package, and that would require using HBM2 as well. I should have realized that even that was too ambitious for a potentially high-volume product. DG1 simply has it's own LPDDR4X memory interface, which makes way more sense. That way they're free to do an MCP with a bog-standard substrate, or with separate packages as they did with Iris Xe MAX.
Yeah, it might even be a cancelled product since it's been sitting in drivers for a long time.
DrMrLordX
Lifer
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@repoman27
Ice Lake-SP was supposed to be out as early as 2019:
www.kitguru.net
It's been delayed multiple times. No idea what that HPC roadmap you saw was on about.
Ice Lake-SP was supposed to be out as early as 2019:
Intel is reportedly delaying the Ice Lake-SP 10nm processor architecture again - KitGuru
Initially scheduled for a release in 2019 and then delayed to 2020, Intel has now pushed the release
www.kitguru.net
It's been delayed multiple times. No idea what that HPC roadmap you saw was on about.
IntelUser2000
Elite Member
- Oct 14, 2003
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From the Ultrabook reviews, both Asus versions beat the Swift in Firestrike but are slower in games. The Flip 13 actually gets almost 5500 points.
Excuse me if I'm skeptical of his results(especially since its all 3DMarks and Furmarks). If the ranks did make that much of a difference, it would be the easiest low hanging fruit that could be picked. Benchmarks show ranks do make a difference but only about 10% at max, and that's in bandwidth, not in actual performance.
And if you got 10% performance gains for 10% bandwidth improvement, you should question it. People forget that 100% scaling doesn't happen except in exceptional circumstances. This implies nothing else matters except bandwidth.
Like I said, if memory mattered that much, then there should be no difference between 1135G7 and 1165G7. Yet there is, and by quite a noticeable amount.
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If RKL@4.2Ghz as below has such ST performance(179 RKL@4.2Ghz vs 166 5950x@4.5Ghz) then ST uplift would be more than 20%. Intel sandbagging something? Need more result to see.....
Gideon
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I'm pretty sure the ST test was ran on with clocks over 5 Ghz.
There have been multiple reports on twitter about clocks at around even 5.5 Ghz:
There was a tweet somewhere listing 4 different reports (5.2-5.6) can't find it right now.
There have been multiple reports on twitter about clocks at around even 5.5 Ghz:
There was a tweet somewhere listing 4 different reports (5.2-5.6) can't find it right now.
Hulk
Diamond Member
- Oct 9, 1999
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I went through this chart again. Cache data comes from https://uops.info/cache.html#CON
If anyone can answer the "?" cells please let me know.
If anyone can answer the "?" cells please let me know.
Attachments
Integer/FP registers is 280/224 respectively for Sunny Cove (and presumably Willow Cove, since AFAICT, the only difference is in the cache hierarchy, not the main core structures). You can find this information in the HotChips ICL-SP presentation: https://images.anandtech.com/doci/15984/202008171735261.jpg
I was intrigued by one parameter in Iceland-SP whose single core x86 SunnyCove has an Out-of-order 384 instruction window, while from the original Iceland it has 352 instructions.
I wonder if this is a mistake or maybe the microcode fixes unlocked inactive parts of the core? Maybe delicate fixes like SandyBridge-IvyBridge or Haswell-Broadwell?
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That is a typo. If you look around on Twitter, you can see that people asked this in person at the presentation and they said there was no change from client Icelake.
uzzi38
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Userbenchmark reports the average clock speed over the entire test. It's more likely the chip is boosting to around or above 5GHz in lighter threaded workloads, then dropping down significantly in the 4 core and above tests.
Hulk
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SAAA
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Precisely. Also funny enough the dual core score is higher than 2x the single core result. Guess it was still ramping up clocks?
1thread 179; 2 threads 368/2 = 184.
Now assuming 184 is at 5.5 GHz as some reported:
184 / 5.5 (max GHz) *4.2 (average GHz reported) *8 (cores) = 1124
The 8 thread result is actually 1115 so, yeah, must be quite high turbo.
5.5 GHz boost or so confirmed, while with 8+ threads the sample must be throttling hard… hitting some power limit?
The local power plant, most probably.
Jokes aside, I don't see how a 5.5GHz single core turbo, on a backported core, on 14nm is coolable either on air or water for 24/7 usage. Skylake already becomes quite toasty in that territory and that core had six iterations of refinement. I know this is a 250w part, but still.
Do we know what cooling they're using?
You can be sure that Intels reference system did use the fastest rank variant but they cannot control the RAM used from OEMs in Retail devices. To make it clear the RAM test here has nothing to do with JZWSVIC. He suspects that the tester there did have 1R x16+1R x8 memory, this is according to him the slowest variant for Irix Xe.
According to JZWSVIC there is a 8.5% Firstrike difference between 1R and 2R DDR4-3200, this is in line with previous generation AMD iGPUs or Iris Pro 580, Intel recommended dualrank (DDR3) a few years ago and claimed a double digits gain in real games for Iris Pro 580. It's not only about the ranks, it's also about LPDDR4 vs DDR4. The only real new thing for me is that even the x8/x16 signal lines seems to make a big difference on Iris Xe which would explain the low scores on some DDR4 machines. All of this didn't matter on Intel iGPUs until now because they weren't bandwidth limited, it was a bigger topic for AMD.
It was on about Intel letting their HPC customers know what their production schedule was:@repoman27
Ice Lake-SP was supposed to be out as early as 2019:
Intel is reportedly delaying the Ice Lake-SP 10nm processor architecture again - KitGuru
Initially scheduled for a release in 2019 and then delayed to 2020, Intel has now pushed the release
It's been delayed multiple times. No idea what that HPC roadmap you saw was on about.
Obviously that June 2018 roadmap wasn't the first one Intel put out that had Ice Lake-SP on it, but it's a little ridiculous to ignore it and instead continue refer back to long term roadmaps published well before the initial failure of 10nm with Cannon Lake when discussing their current production delays. Yes, back in 2016 well before they had even taped it out, Intel thought Ice Lake-SP might be a 2019 product:
But as it stands, they're only 1 or 2 quarters behind the target they announced 2.5 years ago, which is pretty miraculous for Intel these days. And no offense, but next time I'd prefer a link to a site that isn't just making an unsubstantiated assertion with no references.
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Isn't Willow cove L2 still inclusive of the L1 caches? The L3 is exclusive of L2.
MSI Summit 15 2x8GB DDR4-3200 Firestrike: 4045 (High performance mode)
Another confirmation that the low graphics scores are memory related. Cinebench R20 results are great, 2248 first run and 2165 fifth run. In high performance mode it can use ~38W.
The problem is that all 8GB DDR4-3200 modules are single rank by the looks of it, 16GB modules are often dual rank. It means every 2x8GB DDR4-3200 device likely won't get high graphics scores even if the cooling is superior to the ultrabooks with worse cooling/power capabilities.
Another confirmation that the low graphics scores are memory related. Cinebench R20 results are great, 2248 first run and 2165 fifth run. In high performance mode it can use ~38W.
The problem is that all 8GB DDR4-3200 modules are single rank by the looks of it, 16GB modules are often dual rank. It means every 2x8GB DDR4-3200 device likely won't get high graphics scores even if the cooling is superior to the ultrabooks with worse cooling/power capabilities.
DrMrLordX
Lifer
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So what you're really saying is: pretend Intel never planned to release IceLake-SP in 2019? Check.
Intel Rocket Lake and Alder Lake CPUs pictured - VideoCardz.com
A photo of an alleged Rocket Lake-S CPU has emerged. Intel Core i9-11900K? An alleged photo of Intel’s upcoming mainstream desktop processor codenamed Rocket Lake has been posted on Wing Tseung on Facebook. The CPU will feature the same socket as the current Comet Lake-S series (LGA1200). The...
videocardz.com
Videocardz has a picture of Rocket Lake and Alder Lake-S. Just shows just how long Alder Lake-S is.
It isn't, 1.25MB of non inclusive L2 with 20-way 14 cycle latency. Ways are quite important for caches. For example Skylake L2 was 256kb and 4-way, versus same 256kb but 8-ways on previuos gens.
Basically more ways, less conflicts, more performance.
What table overstates is 4 cycle latency for L1 in generations before Sunny Cove. Those 4 cycles were when stars aligned and sun also shined. In most real world cases it was 5 cycle L1 on Skylake and Intel recognized that and made scheduling easier by removing those special cases and having uniform 5-cycle L1.
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