Discussion Intel current and future Lakes & Rapids thread

[Hitman928]

It was either in the first or second quarter financial results. Check the calls and 8k/10qs

How would they report how much ICL inventory they'd sold through Q3 in the Q1 or Q2 earnings report?

 

[IntelUser2000]

Intel Cuts 2nd Gen 'Extended Memory' Xeon Scalable Prices

www.anandtech.com

They need to eliminate the L versions too, and cut it further by $3000. Even then, they'll be behind AMD, because the platform is years behind.

I remember then-server chief Kirk Skaugen saying they regretted crippling Xeon lines to artificially boost Itanium, and vowed not to do that.

I think they need that line of thought again. Here I think is a primary reason why their adjacent(read: non CPU) business has a tremendously difficult time growing.

It's like what they say about Microsoft and Intel are completely true. Microsoft does everything to boost Windows, and Intel does everything to boost CPUs.

The thing is though, when you are behind the competition as they are now, the adjacencies should be given full support. Right now, because the Xeon Platinums only support 12 DIMMs per socket, you end up with a maximum memory capacity of 4.5TB, versus 4TB for EPYC. And 4.5TB for Xeons are only possible if used in the App Direct mode, which requires application support.

Granted, a persistent memory has its own unique advantages, but basically Intel is saying "Please don't use us" when you need to pay $7k extra and have to use their inferior Xeon CPUs.

Pretty much the only technical reason to go for Xeon is the Optane DIMMs, and its being crippled because of the 1) Intel platform that's years behind 2) Price adder.

To fix 1) Future Optane DIMM generations need to ensure it works in all platforms, be it AMD, ARM, Power, or whatever.
To fix 2) There should be zero cost adder for using the top memory capacity configurations.

 

[liahos1]

How would they report how much ICL inventory they'd sold through Q3 in the Q1 or Q2 earnings report?

Because inventory build is typically a quarter before sales/rev rec

 

[tamz_msc]

It was either in the first or second quarter financial results. Check the calls and 8k/10qs

Intel's 'work in process' inventory increased from 4.76bn to 5.61bn while 'finished goods' inventory remained stagnant from q1 to q2. Even though the earnings call mentions that the increase is due to 10nm, there is no way of knowing whether Ice Lake falls under work in process or finished goods. Standing in q2 with sales expected in q3, I would imagine it's the latter. So where is this 500mn figure for Ice Lake coming from?

 

[IntelUser2000]

Standing in q2 with sales expected in q3, I would imagine it's the latter. So where is this 500mn figure for Ice Lake coming from?

Witeken is a big Intel guy, so I don't really doubt his numbers.

But, Intel's Q4 earnings report is in 6 days. So we'll know soon. Even if they don't directly report it, it'll show in the client group's operating margin.

While I will say they are having serious problems with the 10nm process, some claims are pure exaggeration. Like if they are having 20% yields, the cost of production per Icelake chip would be $100, up from $15 it would cost normally.

I don't believe this. I could believe that for Cannonlake, but that caused the product to get canned. They are as a whole too financially conservative to be selling that many chips that cost $100 to produce. You really think they'd be selling a chip that cost *them* $100, in $300 Black Friday systems?! Even their contra revenue wasn't that crazy, and that cost them the entire market.

You can very much have a wafer with nearly flawless dies yet still be difficult to put into mass production. That happens if it doesn't clock to a desired level, if it leaks too much per chip, or it requires too much power at the same frequency.

 

[jpiniero]

While I will say they are having serious problems with the 10nm process, some claims are pure exaggeration. Like if they are having 20% yields, the cost of production per Icelake chip would be $100, up from $15 it would cost normally.

It doesn't actually cost that much. The raw wafer is only like 100-150 bucks and electricity, personnel, etc doesn't really add that much more to it if you are going at full bore and not just screwing around. What "costs" money is depreciating the tools and the fab (that's why TSMC charges 15k a wafer), and the costs to design the chips in the first place. So on the surface they aren't losing money as those costs were already spent whether they produce product or not. Cook the books a little bit and you can hide the depreciation costs... good thing they have a former CFO as CEO, right?

 

[coercitiv]

Witeken is a big Intel guy, so I don't really doubt his numbers.

Not only a big Intel guy, but also the kind of person who values facts over proving a point. He may (still) be wrong, but he doesn't deserve the kind of cheap shots I've seen thrown around here lately.

While I will say they are having serious problems with the 10nm process, some claims are pure exaggeration. Like if they are having 20% yields, the cost of production per Icelake chip would be $100, up from $15 it would cost normally.

I don't believe this. I could believe that for Cannonlake, but that caused the product to get canned. They are as a whole too financially conservative to be selling that many chips that cost $100 to produce.

IMHO Cannonlake was made with less than 20% yields. Remember it was a 70mm2 die and yet they could not make the iGPU work on enough of them to produce a 2+2 SKU.

Moving back to ICL, reductio ad absurdum for production cost doesn't work as intended here. The fabs are built, the machinery cost is sunk, as @jpiniero already mentioned. Even if Intel makes $0 from the sale of an ICL chip, it's still better than nothing and still better for their bottom line. Whether their yields are actually so low is another story entirely, personally I doubt it considering I'm seeing good availability even for G7 chips in local stores, but I don't know what kind of volume Intel is able to pump through their 10nm fabs, so absolute numbers of devices or ICL chips sold is only half the story.

Even their contra revenue wasn't that crazy, and that cost them the entire market.

I really wouldn't dare going back in that purgatory: their contra revenue was EXACTLY that crazy, they paid OEMs more money than they made through sales. It was so bad they even shuffled Mobile and Comm segment in the company structure to hide further losses.

In 2014 Intel reached their goal of 40 million tablets, so they were selling lots of chips yet this is how their balance sheet looked like:

They were selling more chips and losing more money. It doesn't get any more clear on how far Intel is willing to go.

 

[lobz]

Intel's 'work in process' inventory increased from 4.76bn to 5.61bn while 'finished goods' inventory remained stagnant from q1 to q2. Even though the earnings call mentions that the increase is due to 10nm, there is no way of knowing whether Ice Lake falls under work in process or finished goods. Standing in q2 with sales expected in q3, I would imagine it's the latter. So where is this 500mn figure for Ice Lake coming from?

Careful, you're talking to a big time investor.

 

[lobz]

Not only a big Intel guy, but also the kind of person who values facts over proving a point. He may (still) be wrong, but he doesn't deserve the kind of cheap shots I've seen thrown around here lately.


IMHO Cannonlake was made with less than 20% yields. Remember it was a 70mm2 die and yet they could not make the iGPU work on enough of them to produce a 2+2 SKU.

Moving back to ICL, reductio ad absurdum for production cost doesn't work as intended here. The fabs are built, the machinery cost is sunk, as @jpiniero already mentioned. Even if Intel makes $0 from the sale of an ICL chip, it's still better than nothing and still better for their bottom line. Whether their yields are actually so low is another story entirely, personally I doubt it considering I'm seeing good availability even for G7 chips in local stores, but I don't know what kind of volume Intel is able to pump through their 10nm fabs, so absolute numbers of devices or ICL chips sold is only half the story.


I really wouldn't dare going back in that purgatory: their contra revenue was EXACTLY that crazy, they paid OEMs more money than they made through sales. It was so bad they even shuffled Mobile and Comm segment in the company structure to hide further losses.

In 2014 Intel reached their goal of 40 million tablets, so they were selling lots of chips yet this is how their balance sheet looked like:

They were selling more chips and losing more money. It doesn't get any more clear on how far Intel is willing to go.

Alright, no more cheap shots. I can fully support that and am also happy to make amends, but..... in his tweet, he practically states as a fact, that shipped ICL volume is higher than Zen2 as a whole. In the same tweet. I'm still not sure how am I supposed to take any of it seriously after this.

 

[jpiniero]

Moving back to ICL, reductio ad absurdum for production cost doesn't work as intended here. The fabs are built, the machinery cost is sunk, as @jpiniero already mentioned. Even if Intel makes $0 from the sale of an ICL chip, it's still better than nothing and still better for their bottom line. Whether their yields are actually so low is another story entirely, personally I doubt it considering I'm seeing good availability even for G7 chips in local stores, but I don't know what kind of volume Intel is able to pump through their 10nm fabs, so absolute numbers of devices or ICL chips sold is only half the story.

Retail at this point is easily a minority of sales. Most of Intel's sales come through corporate accounts like using a sales rep or something.

To give you an idea, this is Amazon's Top 10 "Best Sellers" for Traditional laptops right now:
- One Ryzen laptop, which happens to be #1 right now using the 3200U
- Two Chromebooks with a 5 year old MediaTek processor, one with a 3+ year old Atom, and one with a Sandy Bridge U processor (seriously)
- Two cheap Windows laptops, one with Bristol Ridge, the other another 3+ year old Atom
- The 2017 MacBook Air
- One laptop with the 8265U and yes one with Icelake, the i5 1035G1.

I imagine most Corporate Accounts are being fed Whiskey Lake. Maybe some lucky ones are getting Comet.

 

[OriAr]

Retail at this point is easily a minority of sales. Most of Intel's sales come through corporate accounts like using a sales rep or something.

To give you an idea, this is Amazon's Top 10 "Best Sellers" for Traditional laptops right now:
- One Ryzen laptop, which happens to be #1 right now using the 3200U
- Two Chromebooks with a 5 year old MediaTek processor, one with a 3+ year old Atom, and one with a Sandy Bridge U processor (seriously)
- Two cheap Windows laptops, one with Bristol Ridge, the other another 3+ year old Atom
- The 2017 MacBook Air
- One laptop with the 8265U and yes one with Icelake, the i5 1035G1.

I imagine most Corporate Accounts are being fed Whiskey Lake. Maybe some lucky ones are getting Comet.

I guess it depends on how much $$$ the corporates are willing to spend, those who spend a lot might get ICL.

 

[OriAr]

Alright, no more cheap shots. I can fully support that and am also happy to make amends, but..... in his tweet, he practically states as a fact, that shipped ICL volume is higher than Zen2 as a whole. In the same tweet. I'm still not sure how am I supposed to take any of it seriously after this.

This depends on Zen 2's volume too, how many Zen 2 units have AMD shipped to date? Would 2 million be a fair estimate? Because if so in the grand matter of things a million or two million is not that much of a difference at all. Given the sales a million ICL units shipped to OEMs sounds about right.

 

[krumme]

What we havnt touched in the process lateness is the effect on the integration between design and process. All the backports - the flexibility in the roadmap.

I cant but think performance will suffer. Its a shame. And they get in more or less the same situation as amd.

The integration advantage is slipping theese days for many areas.

Whats your take on it?

 

[IntelUser2000]

IMHO Cannonlake was made with less than 20% yields. Remember it was a 70mm2 die and yet they could not make the iGPU work on enough of them to produce a 2+2 SKU.

Even with Cannonlake I have doubts if its purely defect density. Reports were that it had problems making the iGPU. iGPU is actually much easier than the CPU portion in terms of defects because it has lots of redundant areas and look more like caches.

When you look at few available reviews for the Cannonlake, it had a very difficult time clocking compared to Kabylake-R parts. At 30% difference in frequency, there's no uarch in the world that would have saved it. The thing is the clock difference nominally were only 10%. But under demanding AVX2 workloads, the gap was huge.

Perhaps the clock could have been higher, but with higher power. Even with zero defects, it immediately makes it not viable for a product.

I think Icelake has issues too, which might be part of the reason some leaks are showing big gains. It might be Tigerlake that has it down pat, because the slide about backporting shows for 10nm, only the 10nm++ is the viable backport option, not the base 10nm, nor the 10nm+.

In 2014 Intel reached their goal of 40 million tablets, so they were selling lots of chips yet this is how their balance sheet looked like:

The contra revenue program wasn't just about giving $10-20 rebates for using their chip. They practically built everything around them for the manufacturers to use. Other than maybe the chassis, the manufacturer could just use Intel's design and brand it their own. So that's why we had few dozen Chinese manufacturers come up with one.

Now Intel makes reference designs for all their products. But the contra revenue program was on a scale unlike anything they'd done before.

 

[lobz]

Even with Cannonlake I have doubts if its purely defect density. Reports were that it had problems making the iGPU. iGPU is actually much easier than the CPU portion in terms of defects because it has lots of redundant areas and look more like caches.

That goes both ways, you could see that also as 'even the GPU part was hard to produce'.

 

[IntelUser2000]

That goes both ways, you could see that also as 'even the GPU part was hard to produce'.

Actually no. It was specifically talking about the GPU.

But as AT's test shows, the product itself was a failure, being slower and having lower perf/watt: https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/7

And it shows doing worse with heavy loads such as with AVX-256 enabled.
If the frequency on the GPU was 30% lower as with the CPU, you'd end up with the 40EU part not being any faster than the 24EU Gen 9.

Now look at how 22nm fared with Ivy Bridge:

The V/F curve is much more steep on the 22nm part. Sure, that's great when you are playing in the notebook power envelope.

Now imagine 10nm in CNL(and in some part ICL) to be worse than that.

Would they really have wanted to put a chip that's 20-30% slower into mass production? Fully knowing that neither in CPU nor GPU it can be put into any sort of premium parts? Or they could save the trouble, rehash 14nm, and wait until Icelake.

 

[Exist50]

Where did you hear that?

A good friend. For that matter, I should add that the entire Oregon Core (capital C) team was liquidated as the culmination of Ocean Cove. Sunny Cove is from IDC, as is Willow Cove, and Golden Cove, and the one after that, and the one after that.

 

[witeken]

I'm sorry man, I can't really take him seriously. Please if you can find this particular piece of info somewhere else, I'm really interested and ready to seriously reconsider what I think.
At first glance, even if what he says is 100% correct, that just means intel managed to dump enough wafers to satisfy a market presence. That says still nothing about yields.
I also thought it was obvious that I didn't literally mean tech demo... sorry if I wasn't clear about that - that goes to @IntelUser2000 too.

As for ICL >= Zen2 in volume?

This would require a whole new Parody & Fantasy World subsection on AT forums.

Slide 24 sir.

https://s21.q4cdn.com/600692695/files/doc_financials/2019/Q1/03.30.2019-10Q-Document_FINAL-FILED.pdf

Commentary: "we intend to qualify the 10-nanometer part in the second quarter. So what that means is in the first quarter, all of our 10-nanometer cost is flowing through cost of sales. When we qualify, it goes on the balance sheet. And then when we sell those previously reserved units in the third quarter, those units go out with no cost. So the dynamics imply low Q1 and a much stronger Q3, but through it all, fairly stable at roughly 60% level."

 

[RetroZombie]

Slide 24 sir.

What's the page number of the document?

By the way, your signature is a little outdated since these days tsmc is a very credible company, it's intel who is unreliable.

 

[tamz_msc]

Slide 24 sir.

https://s21.q4cdn.com/600692695/files/doc_financials/2019/Q1/03.30.2019-10Q-Document_FINAL-FILED.pdf

Commentary: "we intend to qualify the 10-nanometer part in the second quarter. So what that means is in the first quarter, all of our 10-nanometer cost is flowing through cost of sales. When we qualify, it goes on the balance sheet. And then when we sell those previously reserved units in the third quarter, those units go out with no cost. So the dynamics imply low Q1 and a much stronger Q3, but through it all, fairly stable at roughly 60% level."

Why do you assume that all of the 530mn non-qualified products are Ice Lake? Comet Lake also launched in q3, so it must have been 'non-qualified' in q1 as well.

 

[lobz]

Slide 24 sir.

https://s21.q4cdn.com/600692695/files/doc_financials/2019/Q1/03.30.2019-10Q-Document_FINAL-FILED.pdf

Commentary: "we intend to qualify the 10-nanometer part in the second quarter. So what that means is in the first quarter, all of our 10-nanometer cost is flowing through cost of sales. When we qualify, it goes on the balance sheet. And then when we sell those previously reserved units in the third quarter, those units go out with no cost. So the dynamics imply low Q1 and a much stronger Q3, but through it all, fairly stable at roughly 60% level."

Thank you for clarifying that you have no way of actually proving what you wrote in your tweet.

 

[mikk]

A good friend. For that matter, I should add that the entire Oregon Core (capital C) team was liquidated as the culmination of Ocean Cove. Sunny Cove is from IDC, as is Willow Cove, and Golden Cove, and the one after that, and the one after that.

Interesting if true but without a public news I don't know if I could believe this good friend story. In case it's true how can you say Ocean Cove is dead when IDC could continue the work on Ocean Cove?

 

[Exist50]

Interesting if true but without a public news I don't know if I could believe this good friend story.

A very reasonable position to take. All I can say is that time will vindicate me. Indeed, if there's a new architecture day this year, it may not even take very long.

In case it's true how can you say Ocean Cove is dead when IDC could continue the work on Ocean Cove?

The core idea behind Ocean Cove was deemed unnecessary, hence why the team wasn't needed any longer. Future designs may inherit parts of the work on Ocean Cove, but they will not be Ocean Cove. Of course, this was all under BK, so draw your own conclusions about the wisdom of such a move.

 

[OriAr]

A very reasonable position to take. All I can say is that time will vindicate me. Indeed, if there's a new architecture day this year, it may not even take very long.



The core idea behind Ocean Cove was deemed unnecessary, hence why the team wasn't needed any longer. Future designs may inherit parts of the work on Ocean Cove, but they will not be Ocean Cove. Of course, this was all under BK, so draw your own conclusions about the wisdom of such a move.

Was Ocean Cove supposed to be a revolutionary design that Intel felt eventually wasn't needed? Or was it supposed to be a modified Golden Cove?

 

[lobz]

Was Ocean Cove supposed to be a revolutionary design that Intel felt eventually wasn't needed? Or was it supposed to be a modified Golden Cove?

The first.