Discussion Intel current and future Lakes & Rapids thread

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Markfw

Moderator Emeritus, Elite Member
May 16, 2002
25,483
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He clearly
did
Saying its launching on the 7th of January ? Thats a comment ? I would read the article myself and give you an idea of a real comment, but I am busy now. Discussing the hardware is what this thread is about, not making am announcement.

Edit: Look at the 10 or 20 or more posts above it. THEY are discussing hardware.
 

jpiniero

Lifer
Oct 1, 2010
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Intel is currently supply bound. If we take a Coffee Lake HP die as an example, based on how Intel bins them, if the memory controller isn't good for DDR4-2666 2DPC all day long it can only be sold as a lower margin i3/Pentium/Celeron part. If it can't hang at DDR4-2400 it goes in the scrap heap. At least 80% of Coffee Lake HP dies will never be used in conjunction with a Z board, in fact, many of them won't even be sold in LGA packages. They'll be locked in at whatever the validated spec is. Intel needs to set the spec as low as possible to salvage every die they can to alleviate supply pressure, but they can't go too low or they end up penalizing the majority of their customers with lower than necessary memory bandwidth. Even though many Coffee Lake CPUs can support higher memory clocks, they're sold as a DDR4-2666 platform because Intel isn't confident they can make enough dies capable of DDR4-2933 to move the whole product stack up a bin.

This is exactly what we see with Comet Lake S being promised initially as DDR4-2666 with a footnote stating: "Investigating UDIMM 2933 one DIMM per channel (1DPC) support. More details to follow once initial testing on silicon is complete." Intel is right at the edge with their binning and showing their hand.

Any issue might be with boards rather than the controller.
 

lobz

Platinum Member
Feb 10, 2017
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,
One can't link to a much anticipated ice lake notebook release in the ice lake thread? Your level of anti Intel hate must be bottomless.
How do you drag intel into this? It was always the general rule here to elaborate on the content of the links you put into your comment.
 

liahos1

Senior member
Aug 28, 2013
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Saying its launching on the 7th of January ? Thats a comment ? I would read the article myself and give you an idea of a real comment, but I am busy now. Discussing the hardware is what this thread is about, not making am announcement.

Edit: Look at the 10 or 20 or more posts above it. THEY are discussing hardware.
i feel like the standards here are not the same as in the ryzen 4000 speculation thread :coldsweat:

what constitutes a comment?




You have a issue with the moderation? Make an MD thread.


esquared
Anandtech Forum Director
 
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esquared

Forum Director & Omnipotent Overlord
Forum Director
Oct 8, 2000
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i feel like the standards here are not the same as in the ryzen 4000 speculation thread :coldsweat:

what constitutes a comment?
Read the rules. Quit taking this off topic.

edit 08/28/2018:
Do not just drop links without comment. People need to know what are in the links before deciding whether to click on it.
It is your job as a poster to comment on it.
"

Dayman's post is a borderline comment. The link should be elaborated on further.
 

lobz

Platinum Member
Feb 10, 2017
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Lol of course RKL-S is using LGA1200 as well.




Another example from you above, the track record is terrible in this thread.
Terrible example, where he didn't just say 'if I recall correctly' but 'probably' too.

As opposed to Richie Rich who acts as if he was the leading authority of the exact IPC of all different architectures across all ISAs and vendors - past, present, and what's even more impressive: future too.
 

Thunder 57

Platinum Member
Aug 19, 2007
2,647
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Where to start with this one?

You had no clue that the smartphone market is 7x bigger than server, you were lying that servers are more lucrative. Annoyed? Instead, you should be ashamed, all other people here are annoyed with your misinformation.

I'm sure you knew those numbers too before you looked them up :rolleyes: . I already changed lucrative to margins. You either don't understand the difference or conveniently ignored that. If anyone should be ashamed, it should be you because of your ignorance and misinformation.

AMD: Zen 3 is max two threads / core.
You: AMD said SMT2 because SMT4 is a super secret feature that will be a total game changer and they don't want to tip off Intel.

One more time, not that it will change your mind:

amd.png

That +82% IPC advantage of A13 Lightning core is important in context of maximal IPC still available for development of future Intel uarchs (in terms of scalar computation).
  • Ice Lake (Sunny Cove) decreased Apple's advatage to +54%,
  • Willow Cove to +43% (assuming +8% IPC over Sunny Cove)
  • Golden Cove somewhere to +19% (assuming +20% IPC over Willow Cove)
  • Ocean Cove 2022 might finally reach Apple's IPC.
This unveils Intel's 4 years deficit in development. Everyone knows this is result of Intel's extra long SkyLake period, almost six years they were sitting still (2015 - 2020). Same deficit have also generic ARM Cortex cores (A77 IPC is inbetween KBL and ICL) however bringing bigger IPC jumps every year than x86. This is future serious thread for Intel, especially when being squeezed also from AMD.

However Intel has Jim Keller since 2019 so we can expect some nice surprise in 2023. He can finish what he started in AMD - two CPUs (x86 and ARM) based on one shared high performance RISC core.

You claim 82% as if it is fact. No one believes that but you. Also, Jim Keller is a rock star, but he is not a magician. He needs a team of talent and vision. No one man creates a CPU. Does Intel have that? I think so. Their roadmap looks promising if they can get their manufacturing figured out.

And may I suggest this again. You can create your own threads you know. So please stop bringing up ARM all the time in these Intel/AMD posts. May I suggest you create one with the following topic "Apple: Why x86 is doomed".
 

IntelUser2000

Elite Member
Oct 14, 2003
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I didn't realize intel gen 11 gpus had position only shading tile-based rendering (p25). Is that distinct from TBDR?

Search says modern GPUs that are not PowerVR use TBIR, or Tile Based Immediate Rendering. The "D" in PowerVR is deferred.

Intel used TBIR with their Extreme Graphics and GMA 900/950 series. They abandoned it with the GMA X3000, which is what current GPUs are based on, including Nvidia's. PTBR sounds like a variant of TBIR.

There's an incredible confusion over this on the internet, and Intel's Extreme Graphics use of tiles in the description misled many to believe they have used PowerVR tech, when they have not.

Some great article on different methods: https://translate.google.ca/transla...ile-rendering-maxwell-pascal.html&prev=search

In that article, there's also a link describing the differences.

Also in the second article,
Furthermore, when small triangles (which can be processed in a single cycle) cross several tiles, the rasterizer may find itself overwhelmed since it will have to process them once for each tile. This potential loss of efficiency is the reason why Intel and Qualcomm GPUs support IMR in addition to TBR.
Note that the TBDR can lose more efficiency than the TBR when the geometry becomes very complex since the HSR engine will have a harder time determining the visible triangles and potentially become the limiting factor.

Seems like TBDR is a perfect mobile architecture because due to their smaller screen you can lower geometry complexity and still be acceptable quality wise to the user.
 
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DrMrLordX

Lifer
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mikk

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May 15, 2012
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It's not hard to do at all. Look at the datasheet for the chipset. The ballout clearly shows that there are only pins for DMI x4, not DMI x8, therefore DMI x8 isn't possible. You can argue that I can't prove that CMP-H is identical to CNP-H at this juncture, but seeing as there are zero feature changes, identical package dimensions, and the same exact number of balls, it's a pretty safe bet.


In Revision 002 there was DMI x8 for the CNL-PCH! They removed it for some reason.

Chapter 11, Ballout Definition• Updated information for x4 DMI only support. Removed[7:4] lane and x8 width details.
Chapter 38, Direct Media Interface• Updated information for x4 DMI only support. Removed[7:4] lane and x8 width details

Why was there DMI x8 in the first place when they couldn't enable DMI x8 in a later revision of CMP-H? What I said, they won't promote DMI x8 without a supporting CPU, it might be not far fetched!

I cannot find Rev 001 or 002 for Volume 1 but Volume 2 Rev 001 is still available.

Under DMI Configurations Link Capabilities

Maximum Link Width
x1 Link Width
x2 Link Width
x4 Link Width
x8 Link Width

That's why I said you cannot prove your point until RKL-S is ready.
 
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repoman27

Senior member
Dec 17, 2018
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In Revision 002 there was DMI x8 for the CNL-PCH! They removed it for some reason.

Why was there DMI x8 in the first place when they couldn't enable DMI x8 in a later revision of CMP-H? What I said, they won't promote DMI x8 without a supporting CPU, it might be not far fetched!

I cannot find Rev 001 or 002 for Volume 1 but Volume 2 Rev 001 is still available.

Under DMI Configurations Link Capabilities

That's why I said you cannot prove your point until RKL-S is ready.
Well that changes everything. I have a copy of Revision 002 and the x8 width details have already been removed (only Revision 001 had them), however, all of the balls are still listed (as "RSVD").

So this whole time Cannon Point-H has had DMI x8, but has never been paired with a CPU that could do more than x4... Strong work, I stand thoroughly corrected!
 
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mikk

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So this whole time Cannon Point-H has had DMI x8, but has never been paired with a CPU that could do more than x4... Strong work, I stand thoroughly corrected!


I don't even think that CMP-H is a pure renaming of CNL-H even if it's almost identical, it's at least a new stepping or even more. In one of the CML-S slides there was wireless-AX highlighted while CNL-H only supports Wireless-AC. I'm not surprised if there is DMI x8 in a CMP-H datasheet even without RKL-S, but of course they could also wait until RKL-S and then upload a new revision.
 

repoman27

Senior member
Dec 17, 2018
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I don't even think that CMP-H is a pure renaming of CNL-H even if it's almost identical, it's at least a new stepping or even more. In one of the CML-S slides there was wireless-AX highlighted while CNL-H only supports Wireless-AC. I'm not surprised if there is DMI x8 in a CMP-H datasheet even without RKL-S, but of course they could also wait until RKL-S and then upload a new revision.
The slides indicate "Intel Wi-Fi 6 (Gig+) Support (CNVi & Discrete Wireless-AX) Under Evaluation". There is no mention anywhere of CNVio2 support though, so this could be implemented with just a firmware update and a revision of the CRF module. The fact that even discrete (PCIe connected) 802.11ax is "under evaluation" is pretty hilarious. Why wouldn't it work? It's a standard PCIe device for crying out loud.

I would bet on the 400 Series data sheet including DMI x8. I mean, if they actually want their partners to support it on their boards, they would have to.

However, I seriously doubt they invested the resources in a new stepping of CNP-H. That is practically inconceivable. Seeing as they're just renaming a previous PCH design anyway, they could use ICP-H instead, if they have it ready. I've come to find that if I expect the very least from Intel, I am less disappointed in the end.

Edit: I fully derped on this one. I realize now that while I was looking back and forth between the various product briefs and datasheets that I got things completely confused. Even though CNP-H did have DMI x8 capabilities all along that were never exposed, it really didn't matter because the 300 Series chipsets were CNP, and the 400 Series are ICP. I'm guessing Rocket Lake will be paired with 500 Series chipsets based on TGP.

That being said, ICP is an extremely minor revision of CNP—as in practically no changes. The only differences appear to be 802.11ax CNVi support and the removal of the LPC interface from the 495 Series.
 
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jpiniero

Lifer
Oct 1, 2010
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This could be the shape of Intel’s future 10nm desktop Alder Lake CPUs

Regardless of what CPUs it ends up having (heh) I think it does portrend that they are anticipating using chiplets. I am still wondering if the 1159/1200 split is real, and if so does that mean that Intel is trying BGA again and LGA 1700 is the merger between K and HEDT.
 

DrMrLordX

Lifer
Apr 27, 2000
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This could be the shape of Intel’s future 10nm desktop Alder Lake CPUs

Article doesn't seem to say a whole lot, though the author is leaving open the possibility that Alder Lake-S will be Willow Cove rather than Golden Cove. Which seems weird. Everyone else is saying it's Golden Cove. I had originally assumed Intel was using Alder Lake-S as a replacement for Tiger Lake-S (which doesn't exist anymore, and perhaps never did), making it Willow Cove, but but but
 

IntelUser2000

Elite Member
Oct 14, 2003
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Everyone else is saying it's Golden Cove. I had originally assumed Intel was using Alder Lake-S as a replacement for Tiger Lake-S (which doesn't exist anymore, and perhaps never did), making it Willow Cove, but but but

There's some rumors about a Tigerlake Refresh, which could have been renamed Alder Lake.

In desktops, Alder Lake would be a significant advancement over Rocketlake with the move to 10nm process allowing two <100mm2 chips to be used to get to 16 cores. Rocketlake's 14nm Willow Cove cores are too large for two chiplets because even with 8 cores, we'll end up something like 160mm2 and possibly over 200mm2 for 10 cores, not to mention needing a separate die for the I/O and GPU.

7nm in 2021 is going to end up being low volume product, limited to the HPC Xe and likely Ryefield.

If Alder Lake is using Golden Cove, it'll be a third significant iteration under 10nm. That seems less likely.
 

Maxima1

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Jan 15, 2013
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If Alder Lake is using Golden Cove, it'll be a third significant iteration under 10nm. That seems less likely.

Where would ADL-S fit in if RKL-S is Willow Cove and somewhere around early 2021? End of 2021 is definitely Golden Cove.