Discussion Intel current and future Lakes & Rapids thread

[mikk]

I would assume this is Rocket Lake, 32 EUs GT1 is consistent with the driver leak. Imho this is fully Tigerlake ported to 14nm.

 

[jpiniero]

I would assume this is Rocket Lake, 32 EUs GT1 is consistent with the driver leak. Imho this is fully Tigerlake ported to 14nm.

The reason I have some doubt is that it mentions 8 cores max for the H and S parts and not 10 like Comet. You'll notice that they didn't bother to remove Cannonlake so it wouldn't be unusual to add something that won't ever see the light of day.

 

[Ajay]

The reason I have some doubt is that it mentions 8 cores max for the H and S parts and not 10 like Comet. You'll notice that they didn't bother to remove Cannonlake so it wouldn't be unusual to add something that won't ever see the light of day.

Geez, that seems monumentally stupid. With the GPU on it's own chiplet, I would have hoped that bumped RL up to 12 cores. I guess Intel isn't really planning to compete with AMD till 7nm comes along . And we still don't have any visibility into 7nm EUV capabilities or product lineups.

 

[jpiniero]

More than 10 cores isn't happening on the ring. And even using chiplets, if Rocket Lake is indeed using Willow Cove cores it's going to be gigantic on 14 nm and draw a ton of power. Even 10 is extremely pushing it.

 

[majord]

https://pcper.com/2019/09/ice-lake-benchmarks-1065g7-vs-3700u/

Here's a review of the Dell XPS compared to a 3700U.

CPU perf is pretty good really, but given the huge Bandwidth advantage over the ryzen, GPU is underwhelming to say the least.

It’s hard to imagine these wouldn’t be outclassed by Renoir even if it is using old Vega based GPU

 

[mikk]

CPU perf is pretty good really, but given the huge Bandwidth advantage over the ryzen, GPU is underwhelming to say the least.

Ryzen has a huge computing power as well as power advantage.

1.1 TFlop vs 1.8 Tflop/15W vs 25W

Some could say the Vega GPU is underwhelming with this advantage.

 

[Amol S.]

More than 10 cores isn't happening on the ring. And even using chiplets, if Rocket Lake is indeed using Willow Cove cores it's going to be gigantic on 14 nm and draw a ton of power. Even 10 is extremely pushing it.

I have to agree. 9 cores is more likely. Square based package of 3x3 core arangment is possible. In fact 6 core i7 exists, it's just an additional row of 3 cores in my opinion. 10 cores sounds a bit off, 7nm though is possible with size comparison though. At 7nm two rows of 5 cores, would be smaller in size than the 6 core 14nm core i7's that already exist. However the heat produced per cm or mm cubed would be a lot more. However two rows of 5 cores at 14nm is huge for a core series, at that size you probably would find Xeon CPUs.

 

[jpiniero]

I have to agree. 9 cores is more likely.

How would you do 3x3 in a ring? Think about it.

 

[Amol S.]

How would you do 3x3 in a ring? Think about it.

Your question is confusing.... they already have 2x2 CPUs. Core i7 8550U is an example. They make the ring, but then they cut the excess of the ring out in my opinion. Same with an 3x3, just the ring is a bit bigger, bug in the end the output square is smaller a bit. Otherwise how would they be making 12 core Xeon CPUs?

 

[jpiniero]

Your question is confusing.... they already have 2x2 CPUs. Core i7 8550U is an example. They make the ring, but then they cut the excess of the ring out in my opinion. Same with an 3x3, just the ring is a bit bigger, bug in the end the output square is smaller a bit. Otherwise how would they be making 12 core Xeon CPUs?

Skylake Server uses a mesh. The 28 core is 6x5 with two tiles for the memory controller.

 

[Ajay]

IIRC, IB-EP and Haswell-EP used, what, 12 core rings. So that’s not a problem. Size and power are a different issue. That said, I have no idea idea what Intel’s plans are - I just expressed a hope for competitive reasons.

 

[mikk]

IIRC, IB-EP and Haswell-EP used, what, 12 core rings. So that’s not a problem. Size and power are a different issue. That said, I have no idea idea what Intel’s plans are - I just expressed a hope for competitive reasons.

Exactly, also this was made on a 22nm process. It's unknown if they could upscale it on a smaller 10nm node. The mesh was necessary with 20+ core SKUs in mind.

 

[DrMrLordX]

Intel has done ring-of-rings as recently as Broadwell. They could always go back to it, if necessary.

 

[jpiniero]

IIRC, IB-EP and Haswell-EP used, what, 12 core rings. So that’s not a problem. Size and power are a different issue. That said, I have no idea idea what Intel’s plans are - I just expressed a hope for competitive reasons.

And they found it inadequate, also have to factor in the IGP being on the ring.

I would not expect more than 10 on the mainstream socket until 7 nm, and even then who knows.

 

[Ajay]

And they found it inadequate, also have to factor in the IGP being on the ring.

I would not expect more than 10 on the mainstream socket until 7 nm, and even then who knows.

This is Broadwell-EP:

Obviously, their are big issues with the two bidirectional switches and asymmetric location of the PCIe and QPI ports. I don’t think a 12 core ring is likely to be a serious bottleneck, as it is bidirectional.

I hope Intel goes higher than 10 cores on 7nm client CPUs; AMD, having started a new core war, is capturing allot of mind share - even if >90% of users still need no more than 4 cores.

 

[TheGiant]

CPU perf is pretty good really, but given the huge Bandwidth advantage over the ryzen, GPU is underwhelming to say the least.

It’s hard to imagine these wouldn’t be outclassed by Renoir even if it is using old Vega based GPU

well CPU looks good

too bad there arent any words in the article about the fan and how loud is it

14" builds should have enough room to cool even the 25W TDP version

so far at 15W it looks like a generation jump, can't wait for tigerlake and refined 10nm process and ofc the competition from AMD

 

[mikk]

https://twitter.com/x/status/1173590492002562048

Increased L3 cache size for Willow Cove?

 

[Dayman1225]

https://twitter.com/x/status/1173590492002562048

Increased L3 cache size for Willow Cove?

By 50%? Fits with the “Cache Redesign” I guess

 

[TheGiant]

By 50%? Fits with the “Cache Redesign” I guess

I hope cache redesign doesnt mean other changes like mesh on the desktop...

 

[ikjadoon]

What's most interesting is that, despite synthetics showing middling multi-threaded improvements over 15W WHL-U, this 15W ICL-U-based laptop is a good bit faster (9% to 12%) in a more-real-world esque benchmark (though it includes multiple sub-system tests that cloud a a comparison).

Of course, the real world has a well-known single-thread bias. Really curious to see more battery life comparisons, though in typical web-browsing, the laptop display can eat more power than the CPU, so it's all a bit of a mess (i.e., bursty workloads to render pages vs constant display draw).

//

What we don't talk about enough is the enormous amount of noise in testing CPUs on laptop devices: variable fan curves, variable heatsink & chassis dissipation, variable PL2s, variable display panel power draw, variable AC adapters (e.g., 45W vs 65W), variable Speed Shift implementations, variable ambient temperatures, variable lid open angle (i.e., them vents), etc. these all affect CPU performance. Hell, at the size of some laptop heatsinks, even dust could be a factor after extended testing in a dusty environment.

Imagine even half of those variables in an Anandtech desktop CPU test and people would be flipping tables in the comments.

At this point, we should only be comparing laptop to laptop. This is one CPU tested in various models from the same manufacturer, in the same generation, in the same product line:

Eh, well almost the same manufacturer (this std. dev. includes the Lenovo). The PCMark 10 data is much more uniform, but it's testing multiple subsystems and not just the CPU.

/rant

 

[yeshua]

Digitimes reports:

Highlights of the day: Intel stepping up preparations for 7nm manufacturing

Intel in May unveiled plans to launch its 7nm products in 2021, and it is now stepping up efforts towards achieving that goal. It has started placing equipment and materials orders for EUV fabrication processes since August. Meanwhile, TSMC expects 7nm and 7nm EUV manufacturing nodes to be a major growth driver this year, thanks to strong demand chiefly coming from the 5G sector. MediaTek, which reportedly is among the clients using TSMC's 7nm manufacturing node, has unveiled what it calls the world's first sub-6GHz 5G SoC, with volume production on track to begin in Janaury 2020. The handset market still has a lot to offer, as far as HannStar Display is concerned. The LCD panel supplier expects further increases in sales from the handset panel market in fourth-quarter 2019, thanks to strong demand from Chinese clients.

Intel stepping up EUV equipment, material purchases: Intel has started placing equipment and materials orders for EUV fabrication processes since August, and is stepping up its pace of orders, according to industry sources.

MediaTek on track to kick off 5G SoC volume production in 1Q20: MediaTek is on track to enter volume production of its first 5G SoC for sub-6GHz networks in January 2020, having begun sampling the chips in the third quarter of 2019, according to company CFO and spokesman David Ku.

Strong handset panel demand to boost HannStar Display sales in 4Q19: HannStar Display expects its sales for the fourth quarter of 2019 to rise sequentially, buoyed by strong demand for handset panels from Chinese vendors, according to company vice president Wu Hsu-ho.

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[Thunder 57]

By 50%? Fits with the “Cache Redesign” I guess

I hope cache redesign doesnt mean other changes like mesh on the desktop...

You can pretty much count on it. Icelake increased cache sizes but they didn't mention "Cache Redeisgn". Eventually the ring has to go away. Not just that, but the inclusive L3 cache. I expect a non-inclusive L3 in a mesh is what they mean by "Cache Redesign".

 

[Ajay]

You can pretty much count on it. Icelake increased cache sizes but they didn't mention "Cache Redeisgn". Eventually the ring has to go away. Not just that, but the inclusive L3 cache. I expect a non-inclusive L3 in a mesh is what they mean by "Cache Redesign".

If Intel plans on going with a 'chiplet' layout for future higher core count consumer CPUs, the the ring design will still work fine.

 

[Thunder 57]

If Intel plans on going with a 'chiplet' layout for future higher core count consumer CPUs, the the ring design will still work fine.

I suppose they could still use it, but they would incur the "cross CCD" penalty. Not to mention the extra time it would take to get to the I/O die. It wouldn't be as fast as the current ring design.

 

[Ajay]

I suppose they could still use it, but they would incur the "cross CCD" penalty. Not to mention the extra time it would take to get to the I/O die. It wouldn't be as fast as the current ring design.

No, but I don't thing it would be any slower than the "cross CCD" penalty AMD incurs (or, cross CCX). Really depends on the approach Intel takes. I just can't see them going with large monolithic client CPUs anymore (except for laptop).