Question Intel Celestial XE3 discussion - not dead yet

[FlameTail]

Timestamp 20:40

Tom Peterson is asked why Arc Battlemage doesn't have SIMT, and be hinted that a future Xe architecture (Xe3? Xe4?) might add it.

 

[adroc_thurston]

Tom Peterson is asked why Arc Battlemage doesn't have SIMT, and be hinted that a future Xe architecture (Xe3? Xe4?) might add it.

well it does have SIMT.
Better, wave size on Intel uarches is very variable. Should be {16, 32} now?

 

[João Bortolace]

What are some GPU architectural upgrades that might come to Xe3/Celestial?

1. Shader Execution Re-ordering
2. Mesh Nodes and Work Graphs
3. SIMT architecture

Maybe do like nvidea did on Ampere and add FP to INT pipe?

 

[gaav87]

First mention of xe3 in kernel 24.12.2024
D= dgpu / dgfx ?
XE3D = celestial dgpu i assume.

 

[Philste]

So the whole confusion is because Celestial dGPUs will be using Xe⁴, right? That's why some say Celestial dGPU is canceled, they only got the information that Xe³ dGPUs are canceled, so the conclusion was Celestial=canceled.

In reality they probably keep the 2 Year Rhythm and Celestial dGPU are probably targeting late 2026/early 2027 with Xe⁴ and Xe³ is APU only starting H2 25.

 

[mikk]

Too early for Xe4. Nova Lake and Wildcat Lake are on Xe3 and according to Exist50 Razor Lake as well. Alchemist dGPU to Battlemage dGPU was a 2.5 years cadence (A380 launched on June 14th, 2022), mobile versions even earlier. Celestial to Druid sounds like a bigger redesign.

 

[Philste]

Too early for Xe4. Nova Lake and Wildcat Lake are on Xe3 and according to Exist50 Razor Lake as well.

But these are all iGPUs. Strix Halo with RDNA3.5 will launch on the same day as Desktop RDNA4, so what stops Intel from launching Xe⁴ Desktop Cards in early 2027 while iGPUs are using Xe³?

 

[mikk]

Lack of Development time and budget stops them. Two generations within 2.5 years is not realistic. If it's Xe4 it's called Druid and not Celestial. Intel favours iGPUs whereas AMD usually dGPUs.

 

[mikk]

Xe3 is going from 4 to 6 cores for one slice. PTL-H(P) has two 6 core slices for overall 12 cores. This is what Raichu told and we can see this on github as well.

 

[gaav87]

XE3 with larger cache ? If each bit controls two banks instead of one if number of bits did not decrease this could translate to a potentially doubled L3 cache size if fully enabled. Or just diff organization.