Intel Cannonlake SoC will have 4-core, 6-core and 8-core versions

[Arachnotronic]

It's you who are saying that Anadtech reviewers are stupid and got everything wrong because one company (Apple) has chosen another path than the article concludes is the most optimal one from a technological perspective.

Qualcomm is moving away from big.LITTLE at the premium tier to four CPU cores.

 

[vissarix]

I am sure AT knows more than Apple/Qualcomm do

Im sure Apple/Qualcomm knows more then Samsung?!

oh wait...exynos stomps those socs easily...

 

[ShintaiDK]

Im sure Apple/Qualcomm knows more then Samsung?!

oh wait...exynos stomps those socs easily...

Exynos 7240 beats A9?

 

[Nothingness]

Qualcomm is moving away from big.LITTLE at the premium tier to four CPU cores.

This will be the case only if Qualcomm core is competitive, something that is yet to be proven.

And in any case, as you impled, it looks like they'll keep on using b.L in medium and low end parts.

 

[vissarix]

Exynos 7240 beats A9?

on multicore performance yes, in single core no...but we have to consider that A9 is 7 months newer.

Geekbench:

A9: ST 2500
MT 4400

Exynos 7420: ST 1500
MT 5400

 

[ShintaiDK]

on multicore performance yes, in single core no...but we have to consider that A9 is 7 months newer.

Geekbench:

A9: ST 2500
MT 4400

Exynos 7420: ST 1500
MT 5400

So no.

 

[tential]

Cannonlake-E is how far away? Like 2019 at this point?

 

[dark zero]

Exynos 7240 beats A9?

Only on MT. On ST Apple crushes Samsung AND Intel Atom tier.

 

[Fjodor2001]

Exynos 7240 beats A9?

Says nothing about the pros/cons of multi-core and b.L anyway, since different uArches are used in those CPUs. You need to compare same CPU uArch, with different core counts, same OS/SW, and with/without b.L. I.e. exactly what the AnandTech article did. And we all know what conclusion they arrived at, despite that you are in denial of that.

 

[Nothingness]

Only on MT. On ST Apple crushes Samsung AND Intel Atom tier.

Atom is beaten by all recent middle and high-end ARM SoC.

 

[Sweepr]

Xeon-D getting 16C/32T in Q1-2016, now it's official. This pretty much rules out this theory, they are not going back to 8C/16T with 'Cannonlake Xeon-D'.

So Xeon D and Atom C are going from 8 to 16 cores next year while server Skylake-EP/EX will offer up to 28 cores (up from 18 cores right now). All that will happen a lot before Cannonlake's launch. I think there's a strong chance they will increase desktop/mobile core count too (2 years from now).

 

[jpiniero]

It does kind of make sense though to do 80W 16+0 Xeon-D now if the entire Cannonlake mainstream line is SoC. You can almost think of it preparing the Server Xeon E3 customers for what their future looks like. Maybe they will stick some EDRAM on it?

How about this for a lineup? This might be a tad aggressive though.
2+3 (2.5 and 4.5W Core M, 15 and 28W laptop i3, Celeron, Pentium)
4+3 (15 and 28W laptop i5 and i7, 35W desktop i5, Xeons)
6+2 and 6+4 (37 and 47W laptop i5/i7/Xeon, 65W desktop i5 and i7, 80W desktop Xeons, 95W desktop K)
8+0 (45W Xeon-D, Mobile Xeon?)
16+0 (80W Xeon-D)

 

[Sweepr]

Intel is committed to launch Cannonlake in H2-2017:

After the publication of the article, Intel PR reached out to let me know that the listing itself contained "errors" and that it would be taken down (a quick check shows that it has indeed been removed). Intel further clarified that its "first 10-nanometer product is planned for the second half of 2017."

www.fool.com/investing/general/2016/02/16/intel-corp-confirms-first-10-nanometer-product-on.aspx

Desktop, server or mobile first?

Looking at what Broadwell/Skylake delivered, 16 cores @ 45-65W TDP (Broadwell-DE / Xeon-D) and mobile quad-cores starting at 25W TDP (Skylake-H), I'm confident Intel will be able to push higher core counts next year.

Also now that we have 12C/24T-16C/32T Xeon-D I'm almost convinced that this thread's leak is not about 'next-generation' Cannonlake-based Xeon-D.

 

[mikk]

Mobile will surely get the first 10nm chips.

 

[frozentundra123456]

So that is what, 3 years from Broadwell, approximately? Question is, whether there will be any real availability or just poorly implemented, token products like the first six months of Broadwell.

And I am still skeptical of anything more than 4 cores on the mainstream. If they make six or eight cores on the mainstream, what will happen to the HEDT line? Or maybe they will split it, making the mainstream low power, lower performance(per core), while maintaining the high TDP/higher performance per core HEDT line-up.

 

[dark zero]

So that is what, 3 years from Broadwell, approximately? Question is, whether there will be any real availability or just poorly implemented, token products like the first six months of Broadwell.

And I am still skeptical of anything more than 4 cores on the mainstream. If they make six or eight cores on the mainstream, what will happen to the HEDT line? Or maybe they will split it, making the mainstream low power, lower performance(per core), while maintaining the high TDP/higher performance per core HEDT line-up.

HEDT line wasn't supposed to exist, it will just get eliminated for good.

 

[Sweepr]

Mobile will surely get the first 10nm chips.

Makes sense, but the new Xeon-D should also be one of the first 10nm products.

 

[Aristotelian]

HEDT line wasn't supposed to exist, it will just get eliminated for good.

I asked a similar question (to the one your post responded to) in the Broadwell thread, but since you're stating that with so much conviction: why wasn't the HEDT line supposed to exist? Is the market between full out server cpus or mainstream user cpus so small? I wouldn't think so.

 

[jpiniero]

So that is what, 3 years from Broadwell, approximately? Question is, whether there will be any real availability or just poorly implemented, token products like the first six months of Broadwell.

Probably more the later. Although if they are doing phones I imagine they will try to get it out first and would try to get tablets and ultrabooks out in time for Holiday shopping season. Would not be surprised if the laptops and 'desktop' products are sometime in Jan-Feb 2018 though.

No idea about Xeon-D, depends on yields look like. How high in core count do they want to go?

And I am still skeptical of anything more than 4 cores on the mainstream. If they make six or eight cores on the mainstream, what will happen to the HEDT line? Or maybe they will split it, making the mainstream low power, lower performance(per core), while maintaining the high TDP/higher performance per core HEDT line-up.

Well, my theory was that the mainstream would be BGA-only low power SoC. Clock speeds would obviously depend on what they could hit on the low power process but the main focus is the voltage-per-clock speed at the lower to medium end.

The HEDT would be the high power socket replacement (but only available at $400+) using a core-less mainstream die as it's PCH. The timing would make sense since it could be sometime in the middle of 2018.

 

[USER8000]

I expect it will be 10NM Atom and a few low powered 10NM Core i3 CPUs in H2 2017 and with 1H 2018 when the desktop CPUs launch.

 

[Nothingness]

Cannonlake command-line support has been added to LLVM: https://github.com/llvm-mirror/clang/commit/4ac9f2c9a40dae984066de241429c5a7a3472346

The interesting part is the list of enabled features, which is a superset of what they call SkylakeServer. In particular that means AVX-512, which would be very good news.

 

[ShintaiDK]

I dont think end users will get AVX512, because the use case is close to zero. And people isn't willing to accept the frequency change or the TDP. But its coming to servers and perhaps HEDT.

 

[Nothingness]

I dont think end users will get AVX512, because the use case is close to zero. And people isn't willing to accept the frequency change or the TDP. But its coming to servers and perhaps HEDT.

Don't break my dreams, I want AVX-512 without having to pay WS prices :biggrin:

 

[jpiniero]

I dont think end users will get AVX512, because the use case is close to zero. And people isn't willing to accept the frequency change or the TDP. But its coming to servers and perhaps HEDT.

The Linux code sure makes it look like it has all of AVX-512 plus some new ones. Plus SHA which might be useful to some people. Of course it might be disabled or some other method on mainstream parts. Also interesting that while they split Skylake Client and Skylake Server they did not do that for Cannonlake.

case CK_Cannonlake:
setFeatureEnabledImpl(Features, "avx512ifma", true);
setFeatureEnabledImpl(Features, "avx512vbmi", true);
setFeatureEnabledImpl(Features, "sha", true);
setFeatureEnabledImpl(Features, "umip", true);
// FALLTHROUGH
case CK_SkylakeServer:
setFeatureEnabledImpl(Features, "avx512f", true);
setFeatureEnabledImpl(Features, "avx512cd", true);
setFeatureEnabledImpl(Features, "avx512dq", true);
setFeatureEnabledImpl(Features, "avx512bw", true);
setFeatureEnabledImpl(Features, "avx512vl", true);
setFeatureEnabledImpl(Features, "pku", true);
setFeatureEnabledImpl(Features, "pcommit", true);
setFeatureEnabledImpl(Features, "clwb", true);
// FALLTHROUGH
case CK_SkylakeClient:
setFeatureEnabledImpl(Features, "xsavec", true);
setFeatureEnabledImpl(Features, "xsaves", true);
setFeatureEnabledImpl(Features, "mpx", true);
setFeatureEnabledImpl(Features, "sgx", true);
setFeatureEnabledImpl(Features, "clflushopt", true);
// FALLTHROUGH

 

[DrMrLordX]

If it's not too much trouble, could you provide a brief explanation to the non-coding readers what is a switch statement and what is the relevance of fallthrough in this particular circumstance? I know what's going on, though everyone else might not . . .