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Intel Broadwell Thread

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DrMrLordX said:
They are probably selling chips that came off of OEM trays.

btw who said it was going to be $480 for the i7-5775C? That's insane if true.
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That does seem pretty excessive. It's obviously not an off the shelf part but the list release price of the 4770R was only $392 VS $339 for the 4770k. Sub-$400 might be justifiable, but not almost $500.
 
We will see more pricing next week for sure, but they they seem to be around 450-500.

ncixus.com has it for 500.

I'll keep looking for BX80658I75775C throughout next week.
 
If they are going to actually sell at that price, we must be talking about a fairly powerful iGPU. Having read a couple of Broadwell NUC reviews, I didn't really think this was going to be the case, but maybe when these parts are unleashed from low TDP requirements they will surprise us.
 
For NUCs it can be ok but for the ockers it shouldnt be a good deal, the 4.8 screenshot is either under nitrogen or if on air voltage is not visible since something like 1.5V would be needed to get this frequency in such cooling condition, and in a cool room, 18.8°C in the pic with the screen...
 
It is good to see some shops carrying it for less than $500. What we have are etailers gouging at prices far above apparent MSRP.

Abxw, how do we know it was under LN2? I've heard the claim, but all the pics show it with a tower cooler in a push/pull configuration. The voltages WERE stupidly-high for the 5 ghz boot . . . definitely not what you want for your daily driver.
 
I think it's a suicide run on air. Few will reproduce it, but it is perhaps indicative that clocks might not be as bad as we think.
 
DrMrLordX said:
It is good to see some shops carrying it for less than $500. What we have are etailers gouging at prices far above apparent MSRP.

Abxw, how do we know it was under LN2? I've heard the claim, but all the pics show it with a tower cooler in a push/pull configuration. The voltages WERE stupidly-high for the 5 ghz boot . . . definitely not what you want for your daily driver.
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The screen display 3.3GHz, what is suspicious is that for on air the voltage is actualy not...high enough since the 14nm require 15% more voltage at the same frequency, at least with the available datas of BDW up to 3.1.

In the most favourable part of their curves CPUs voltage scale like the root square of the frequency, since a BDW need 1.110-1.148V at 3.1GHz it s not complicated to compute that at 5.0 the required voltage is Sqrt(5/3.1) x (1.110-1.148) = 1.410-1.458V, that s exactly what is displayed in the CPUZ screen...

What is even more suspicious is that the 22nm process diverge notably from this ideal curve starting at 3.5, from 4.0 to 4.4 a 4770K TDP increase by 50% while a perfect curve mandate 21%, from 3.0 to 4.0 the exponent of the curve has transited sharply from 2 to 4, i dont think that the 14nm could maintain a cubic curve up to 5.0, let alone said ideal square law...
 
So basically, you're speculating . . . nobody has shown screens of LN2 pots, or any of the insulation necessary to stop a board from frying itself due to condensation while under LN2. I'm going to agree with Crashtech on this one.
 
DrMrLordX said:
So basically, you're speculating . . . nobody has shown screens of LN2 pots, or any of the insulation necessary to stop a board from frying itself due to condensation while under LN2. I'm going to agree with Crashtech on this one.
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At this frequency and with 1.419V it wont even boot, a suicide run would require 1.625V to make it effectively run on air for a fast screen capture but this is surely too high for 14nm, hence the need of LN2, it s not speculations otherwise there would be 4C Broadwell DTs at 4.0+ and 65W TDP all over the place..

HW need 0.976V at 2.9 while BDW is at 1.050V, do you expect that at 5.0 the latter will need less voltage than the former..?.

Idealy at 5.0 Haswell would require 1.28V, yet to get 5.0 for sure require 1.4-1.5V, and BDW/SKL need said 15% more from the start.
 
The process is a very different one for those chips, they have the dense soc variant (probably used in core-M and xeon-D) while for quad cores it's pretty certain they are using a high performance variant.

Abwx how can you deduce they have the same voltage scaling and actually why it should be similar to 22nm? They had all those delays till now, a new stepping and finally there might be a good process optimized for high frequency too.

Indeed the proof of this should be the fact that Skylake is launching with 4GHz base from start while on 22nm only recently Haswell refresh got that (and we were lucky, sincerely).

Also if they are going to release a Skylake refresh (from another leaked roadmap) what do you expect them to do on the top part: add AVX, GT4?
I'm seriously expecting a bump in clocks, that or they will stop a 10 years long streak of increasing performance on quad cores (at stock speed obviously).
So some 4.2-4.4GHz base to get that 5-10% every year, regardless of overclocking potential.
 
SAAA said:
Abwx how can you deduce they have the same voltage scaling and actually why it should be similar to 22nm? They had all those delays till now, a new stepping and finally there might be a good process optimized for high frequency too.
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This is straightforwdly deducible from the available numbers, 14nm process induced tranbsistors are not faster than 22nm ones, this can be deduced from the higher voltage at 3.0.


SAAA said:
Indeed the proof of this should be the fact that Skylake is launching with 4GHz base from start while on 22nm only recently Haswell refresh got that (and we were lucky, sincerely).
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The proof is that they had to accomodate this with a 95W TDP instead of 84-88W.

SAAA said:
Also if they are going to release a Skylake refresh (from another leaked roadmap) what do you expect them to do on the top part: add AVX, GT4?
I'm seriously expecting a bump in clocks, that or they will stop a 10 years long streak of increasing performance on quad cores (at stock speed obviously).
So some 4.2-4.4GHz base to get that 5-10% every year, regardless of overclocking potential.
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That s another debate but in short there will be no frequency bumps, more throughput is possible at acceptable perf/Watt only with more cores, the ISA extensions and other such routes are doomed to fail as throughput increase lineraly in respect of power with core count while it increase as a square root with frequency and ISA extensions, that s all the reason of the DT market dying since a basic PC has now less throughput than Mediatek s latest phone chip...
 
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Abwx said:
they had to accomodate this with a 95W TDP instead of 84-88W.
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The increase in wattage could be down to the absence of the FIVR (I'm assuming putting it on the chipset nets in a decrease in power efficency) and Skylake's IGPU could consume more power the Haswell's.

Either way, this is all speculation since none of us have access to the hardware to test and the products are still under NDA.
 
Dave2150 said:
The increase in wattage could be down to the absence of the FIVR (I'm assuming putting it on the chipset nets in a decrease in power efficency) and Skylake's IGPU could consume more power the Haswell's.
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Less hardware increase power comsumption and/or losses..?.

crashtech said:
Broadwell has FIVR,but Skylake won't.
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That only aggravate the case since the IVRs TDP will be extracted from the chip and deported to the usual external VRMs, otherwise they would have had to set the bar at 100-105W instead of 95W...
 
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Dave2150 said:
The increase in wattage could be down to the absence of the FIVR (I'm assuming putting it on the chipset nets in a decrease in power efficency) and Skylake's IGPU could consume more power the Haswell's.
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Maybe. The FIVR's published efficiency numbers for med-high voltages were mediocre compared to a good external regulator, so if anything, desktop Skylake will be more efficient under sustained load. FIVR's main advantage is for better DVFS, which is needed for mobile, so I expect that we'll see its return in the future.

Abwx said:
That only aggravate the case since the IVRs TDP will be extracted from the chip and deported to the usual external VRMs, otherwise they would have had to set the bar at 100-105W instead of 95W...
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Maybe. Just because there's a thermal envelope doesn't mean that the device actually fills it up. For example, there's no way the 4790's power consumption is only 4W higher than the 4770's.
 
Abwx said:
Less hardware increase power comsumption and/or losses..?.
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I'd assume the absence of the FIVR on Skylake would mean the 'standard' VR would be less efficent, since it's not on die and isn't able to send as low voltages to each core.

Pretty logical that the CPU would end up receiving slightly more voltage for any given task, compared to the fine degree of voltage control that Haswell/Broadwell with the FIVR are capable of.
 
Dave2150 said:
I'd assume the absence of the FIVR on Skylake would mean the 'standard' VR would be less efficent, since it's not on die and isn't able to send as low voltages to each core.

Pretty logical that the CPU would end up receiving slightly more voltage for any given task, compared to the fine degree of voltage control that Haswell/Broadwell with the FIVR are capable of.
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Yeah, that is why HW presented almost a regression in perf/watt vs IB on the desktop space under load....


Oh, wait...

The FIVR was always about the mobile space and idle power consumption savings, not load scenarios and in the end, listed TDPs.
 
Abwx said:
At this frequency and with 1.419V it wont even boot, a suicide run would require 1.625V to make it effectively run on air for a fast screen capture but this is surely too high for 14nm, hence the need of LN2, it s not speculations otherwise there would be 4C Broadwell DTs at 4.0+ and 65W TDP all over the place..
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What are you going on about? The Kitguru article clearly states that he was able to boot it @ 5.0 ghz with 1.419v vcore. Am I supposed to take your extrapolative analysis over what they're reporting as fact?

You're completely ignoring leakage current and its influence on voltage requirements. If Intel has figured out how to respin their 14nm process so that it has lower leakage current than their 22nm process and a higher clockspeed "wall" than Haswell, then more power to 'em. One of the telltale signs of low leakage is the requirement for higher voltage at the same clockspeed without increasing overall power draw, since the current is lower than it would be on a higher-leakage part.

Idealy at 5.0 Haswell would require 1.28V, yet to get 5.0 for sure require 1.4-1.5V, and BDW/SKL need said 15% more from the start.
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So a guy gets an ES (which is what we've all been waiting for someone to do), puts it through the paces, boots it at 5 ghz, and this is all you've got to say about it? Come on, man! You are basically saying that Lam, HKEPC, Kitguru, and everyone else reporting on this story are boldface liars.

SAAA said:
The process is a very different one for those chips, they have the dense soc variant (probably used in core-M and xeon-D) while for quad cores it's pretty certain they are using a high performance variant.
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That is my expectation. This chip is the first we've seen of it. It's what Intel needed to do to save face, and fortunately for consumers, they seem to have done it. We'll know more once retail samples start shipping.

Indeed the proof of this should be the fact that Skylake is launching with 4GHz base from start while on 22nm only recently Haswell refresh got that (and we were lucky, sincerely).
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Pretty much, yeah.
 
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