*Some* consoles are, but unless it's designed as an exclusive for a particular console most multi-plat engines are scaled up from the weakest platform.
*Some* consoles are, but unless it's designed as an exclusive for a particular console most multi-plat engines are scaled up from the weakest platform.
The PS5 and XBOX Series S/X which have been out almost 4 years since November 2020 are both 8 cores and 16 threads Zen 2 CPUs.
The consoles not 8 cores and 16 threads are the near 11 year old PS4 and XBOX One which are like end of life now and have been for a couple of years at least.
At least series x gives a possibility to use smtcpu @ 3.6ghz or without smt and 3.8ghz. Which operating mode is more popular?
I never knew that!
WHAT???
Curious to know why Microsoft would expose this option. It makes testing games twice as hard (one set of testers testing with SMT and other without SMT). Also, some games may only have been developed for the higher frequency so they might tell the user at startup to turn SMT off. Does the SMT on/off switch require a restart or is it somehow dynamic?
WOW. That's the single best crazy bit of console info I've ever heard!
@SteveGrabowski , know anything about this?
It's set by the game developers I thought. So it wouldn't require more testing. Just ship whatever you tested.
Hail The Brain Slug
Diamond Member
- Oct 10, 2005
- 3,712
- 2,972
- 136
This hardware level config is a game-specific option set by the devs as part of profiling and optimizing for the console. It's not end user exposed.
But then it has to be dynamic SMT or the OS prevents scheduling of threads on the virtual cores to allow the physical ones to boost higher.
Hail The Brain Slug
Diamond Member
- Oct 10, 2005
- 3,712
- 2,972
- 136
I'm sure PS5 has similar hardware configuration knobs and levers for the devs to configure for their specific game. I haven't done any of that for PS5 so I am not familiar with what they may expose to the devs.
Page 557 - Discussion - Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
Page 557 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
forums.anandtech.com
This really opens the door for Bartlett Lake!
Can't wait!
Hopefully!
And AVX-512 enabled would be icing on the cake. No heterogeneous core crap!
12 cores with HT disabled should cover almost 99% of multithreaded game engines' needs.
SteinFG
Senior member
- Dec 29, 2021
- 709
- 830
- 106
Bartlett lake is not using new core. It's a 12-core raptor lake chip with no e-cores. It's 12c/24t because raptor cove has HT enabled
NTMBK
Lifer
- Nov 14, 2011
- 10,398
- 5,629
- 136
It's not getting the core from Arrow Lake? Well that sucks
Doubt they want to pay for more TSMC N3B, and if they were to try to back port the new P cores to Intel 10/7nm, would they fit?
Yes but most enthusiast gamers will disable that HT to get slightly higher ST throughput.
They could always release a 32 core Skymont on LGA1700.
Backporting that to Intel 7 should be easier than doing the same for Lion Cove.
Backporting that to Intel 7 should be easier than doing the same for Lion Cove.
Presumably the original reason for doing this was to do a Xeon E they could sell and at volume. And they pretty much want a P core only die.
Plus they wanted AVX-512.
Ah. That makes more sense. So they sell the good dies as Xeon and the leakier ones end up in LGA1700 socket.
48:46
Appears Zen 6 may be 12 core CCDs. Though hopefully on one CCX and then we are on.
Though 2 years at least wait as late 2026 or early 2027 per rumors only a week or so ago.
adroc_thurston
Diamond Member
- Jul 2, 2023
- 5,406
- 7,576
- 96
Maybe.
12c ring CCX is indeed real at least for Venice Classic.
Sounds great, but would they have to give up per core performance (i.e. make the cores smaller/omit features/sacrifice IPC) to squeeze 12 cores into one CCD? I dont know what process Zen 6 is on, and how much it will increase the transistor budget without increasing die size.
adroc_thurston
Diamond Member
- Jul 2, 2023
- 5,406
- 7,576
- 96
It's an N3 freebie deal. Like .66x chip scaling means you get to stuff more cores while maintaining the same ~70-80mm^2 CCD area.
TRENDING THREADS
-
Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)- Started by DisEnchantment
- Replies: 24K
-
Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
- Started by Tigerick
- Replies: 19K
-
-
-
Facebook
Twitter