• We’re currently investigating an issue related to the forum theme and styling that is impacting page layout and visual formatting. The problem has been identified, and we are actively working on a resolution. There is no impact to user data or functionality, this is strictly a front-end display issue. We’ll post an update once the fix has been deployed. Thanks for your patience while we get this sorted.

News Intel Bartlett Lake-S: up to 12P-Core or up to 8P-Core +16E-core

Page 16 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
It can't cause that's fused off from factory
Are we sure that's the case for Bartlett Lake S?
I get that the edge SKUs that share the same wafers as Raptor Lake SKUs would have those capabilities fused off, but this 12P variation has no consumer equivalent.


For this particular product. that's an absolutely idiotic move. The circuits for AVX-512 are already there. It's just validation overhead for something that could be sold as a low end workstation Xeon product with a markup.

Not only that, but the competition already has 16-core "P-only" products with AVX512 enabled on the market and for a similar price range. They wouldn't be cannibalizing on their higher end products, they's simply be better equipped to compete.
 
Are we sure that's the case for Bartlett Lake S?
I get that the edge SKUs that share the same wafers as Raptor Lake SKUs would have those capabilities fused off, but this 12P variation has no consumer equivalent.
They use the client core variant which wasn't validated for AVX-512
 
AVX-512 Xeons are next year you would be able to get 32 E or 16 P core Xeons from the NVL compute tiles.
 
Then my point is that. If the feature isn't fused off (because there's no consumer equivalent that requires it) then it might be possible to enable it by messing with flags the BIOS.
Only for the early batches after that they were fused off in HW
 
My point is: the needed transistors are still in the Raptor lake P cores. There were no show stopper bugs found in the Alder Lake AVX-512 implementation for those people that have kept their processors from having it disabled. Validation shouldn't be a major issue. This is a low hanging fruit for a processor that's essentially a retread of established IP blocks that could have served as needed product differentiation and a value-add. If they chose not to enable it, that's fine. Doesn't mean that I can't be disappointed by a product that I likely will never actually buy.
 
The original Alder Lake should have had the AVX-512 validated. The P core only Core i5 models would have had it enabled by default.
I don't think it actually shipped, it was BIOS hack only from day one, no? Which is why Intel kept whacking to disable it - if it was in product specs, they would not be able to do that so easily.

It's actually possible it failed validation and that is one of the reason they were not willing to allow unofficial usage.
 
I don't think it actually shipped, it was BIOS hack only from day one, no? Which is why Intel kept whacking to disable it - if it was in product specs, they would not be able to do that so easily.

It's actually possible it failed validation and that is one of the reason they were not willing to allow unofficial usage.
AVX-512 on Alder Lake required some early Microcode version, but I think it was working from Day One at least for a few months after it became known you needed to disable E Cores.
Oh also, that it gets into the product specs means nothing. How many times Intel disabled TSX post shipping with no compensation? I recall the very first time affecting all Haswells and some Broadwells, then a later one in 2021 that removed it on almost everything Skylake based.
 
Those TSX kills were a big deal though, exactly because it was changing the specs.

With Alder Lake iirc Intel floated support before launch when it was kind of announced that it will be able to run by disabling E-Cores. But that got scrapped before launch and the official spec was that it doesn't have AVX-512.

IIRC mobo BIOSes kept exposing it when E-Cores were disabled (my bad calling it a BIOS hack, that was misleading) despite. But at launch and ever since it was unofficial. IIRC I was surprised when Intel actively tried to suppress it but they did so, for whatever reason.
 
Those TSX kills were a big deal though, exactly because it was changing the specs.

With Alder Lake iirc Intel floated support before launch when it was kind of announced that it will be able to run by disabling E-Cores. But that got scrapped before launch and the official spec was that it doesn't have AVX-512.

IIRC mobo BIOSes kept exposing it when E-Cores were disabled (my bad calling it a BIOS hack, that was misleading) despite. But at launch and ever since it was unofficial. IIRC I was surprised when Intel actively tried to suppress it but they did so, for whatever reason.
You can still disable the E cores it's just AVX-512 won't be activated on new bios
 
I just finished a two hour Hell Let Loose session and the game feels much smoother than with my tuned 14900KS+8400C4 profile. The average FPS is 10-15% higher, but the 1% lows are much lower. So this 12 P core configuration addresses one of the causes of stutter which is either less P-cores or or thread directing with Ecores present, or a combination thereof. However, the 1% lows are like 70 instead of 90-100 with the 14900KS.

Well well well. So Intel purposely demoted this gaming ready chip for the sake of keeping Arrow Lake relevant. What utter morons. Should've just released this chip and lesser P-core only variants and skipped Arrow Lake. The stupid decisions this company makes will be the legends of history books.

Obviously the 1% lows suffer because of DDR5-5600.
 

Well well well. So Intel purposely demoted this gaming ready chip for the sake of keeping Arrow Lake relevant. What utter morons. Should've just released this chip and lesser P-core only variants and skipped Arrow Lake. The stupid decisions this company makes will be the legends of history books.

Obviously the 1% lows suffer because of DDR5-5600.
Well you can run games on them with W series boards iirc i want someone to test that and JEDEC would be fine
 
I'd say this is job for some of those large youtubers that can pay such stuff from their ad revenue...

Probably just needs some time for some of them to provide.
 
  • Like
Reactions: 511

Arrow Lake Refresh being put to shame by an "industrial" CPU.

SMH

Also, the future of 8 P-cores is starting to look bleak. Intel is gonna make another big mistake with Nova Lake by shipping it with only 8 P-cores max per compute chiplet.
 

Arrow Lake Refresh being put to shame by an "industrial" CPU.

SMH

Also, the future of 8 P-cores is starting to look bleak. Intel is gonna make another big mistake with Nova Lake by shipping it with only 8 P-cores max per compute chiplet.
Just forget about NVL.
Period.
 
how long till forget about Unified core?

I hope that never comes
At this point, only a misstep from AMD can help Intel get ahead.

They messed up really bad by letting Jim Keller leave. And the sad thing is that no one cares. Not even the people here.

I wonder if adroc cares 😛
 
Back
Top