It's typically a lot more efficient than DDR3 thanks to running at lower voltages.
GDDR5 is specified at 1.5V and 1.35V just like DDR3 (latter is often called DDR3L, is becoming more common even in laptops). You can also find both over volted in some parts.
I don't think there's anything to support it using more W/bit/S (power for a given bandwidth), the problem is if it's providing twice the bandwidth all the time. You end up with twice the data per pin and it uses more power for bandwidth you often won't need. This will generally just apply when the memory is used but it's still an impact.
As far as I'm aware normal PCs with either DDR3 or GDDR5 system memory is not going to be employing dynamic frequency scaling, much less dynamic voltage. Someone please correct me if I'm wrong about this, but I don't think this is something you will find in the memory controller.
Idontcare said:
The only question you've have to ask yourself is "why wasn't this the plan for Llano?"
I give AMD credit for knowing enough about what they do as to assume that they knew in advance that Llano, and its successors, would be critically dependent on ram bandwidth (and limited as such by DDR3).
Not sure if that was supposed to be a rhetorical question, but Kaveri will need the bandwidth way more than Llano. Because its compute, TMU, etc count increases far more than the system bandwidth increase by using faster DDR3. Llano was bandwidth limited a lot (most? all??) of the time but if using faster memory only gets you 10% more performance there and 100% more performance here then it becomes a very different scenario...
As I recall the actual performance of Rambus, especially on northwood P4 systems, was actually really good, and if it wasn't for the stupid licensing issues and price I think it would have worked out fine.
It looked good compared to SDR SDRAM which was the first alternative offered for lower end platforms (Celerons) but the real comparison was with DDR, when those chipsets inevitably came out.
RDRAM had better bandwidth but the latency was worse, and as usual for general CPU problems latency was more sensitive. This was especially true for Pentium 4 with its high clock speeds and typically low IPC. So RDRAM looked great on synthetic memory bandwidth tests but for real world applications wasn't nearly as useful and sometimes even worse.
Here's a good comparison:
http://techreport.com/review/3231/pentium-4-ddr-chipsets-compared
You can see the top positions in the benchmark is usually taken by SiS's chipset, although the differences between the DDR chipsets and i850, and often even i845 are usually not that big. You can see in hindsight that RDRAM wouldn't have been a good decision even if it was cheaper. It's true that i845D wasn't really that impressive, but my guess is that Intel was scrambling to get it to market once they realized i850 + RDRAM was a bust and SiS and VIA was eating their lunch with cheaper and better alternatives. Had Intel stuck with DDR from the start they would have had time to do a better chipset. Not sure what DDR availability was for Pentium 4's launch, I just know that you AMD's DDR supporting 760 chipset launched the same month, so it should have been realistic.
Intel already got burned by i820 on Pentium 3, and with Pentium 4 they had to put in a big financial stake subsidizing it just to avoid subjecting people to the big retail price Rambus wanted (they had bundles including memory with the CPU).