Question Intel and AMD form x86 Ecosystem Advisory Group

[Covfefe]

It looks like the group is alive and well and making noticable progress:

Advancing x86, Together

Advancing x86, Together Since its inception, the x86 Ecosystem Advisory Group (EAG) has been a driving force in shaping the future of x86 computing. Fueled by a deep – and somewhat unexpected – collaboration between AMD, Intel, and key industry partners, the group has made remarkable strides in alig

www.linkedin.com

x86 Ecosystem Advisory Group Aligning On FRED, AVX10 & APX - Phoronix

www.phoronix.com

There the AMD executive commented on the x86 EAG early successes:


It does look like future AMD processors will support FRED, APX and AVX10 (which is just glorified AVX-512 essentially) with more announcements to come (hopefully also from AMDs side)

It's cool that the two rivals are working together to advance x86. Intel and AMD have adopted each other's new instructions in the past, but AFAIK they haven't worked together on new instructions. It's a unique situation, almost democratic.

I'm cautiously optimistic, but I could also see this falling apart in a few of different ways.

• AMD adds a new extension that Intel doesn't approve of. Intel releases their competing version, AMD leaves group. (Or vice versa)
• Leadership at one of the companies decide its bad business to help their competitor and leave the group.
• Progress on new extensions is bogged down by deliberation.
• Intel and AMD are pressured by industry partners into adding extensions that are beneficial in certain usecases but are bad for the overall x86 ecosystem.

 

[511]

It does look like future AMD processors will support FRED, APX and AVX10 (which is just glorified AVX-512 essentially) with more announcements to come (hopefully also from AMDs side)

Zen 7 at minimum Intel should delegate the work to AMD since they are the leaders in Server 🤣🤣

 

[regen1]

Advisory Group seems to be working well.
Even before the formation of x86 advisory committee AMD was working on AMX.
Both Intel and AMD should have a successor to AMX already discussed in the committee.
Don't know whether it will be exact same implementation or somewhat different on both sides, also if it would be named the same. The successor should come to both client and server. Guessing Titanlake or later for Intel and Zen7 or later for AMD
Heard AMX development might freeze post DMR, not sure(They perhaps may have it in Silicon further than that for consumer support and there might not be more development/addition inside the AMX instructions???).
Haven't got any definite proof on that yet.


Also this
It has been redacted since from Intel Docs.

Disclaimer: Some of the above can't be confirmed and some are speculative/hearsay and future plans can change, don't take it as 100%.

 

[511]

Don't know whether it will be exact same implementation or somewhat different on both sides, also if it would be named the same. The successor should come to both client and server. Guessing Titanlake or later for Intel and Zen7 or later for AMD

I doubt the committee would decide to get this on cliennt

 

[regen1]

I doubt the committee would decide to get this on cliennt

When it was just the current sort of AMX implementations I had my doubts for client. You could be right, the successor too might not come to client. I have no idea. But some think it might at least on AMD's side.
Have to factor the jump from Intel 3 to A14 and 14A would be big(density-wise) and design of the new co-processor/engine itself could be more area-efficient. May be during A10 or 10A era. Again just speculations.
I am not sure if the committee is that focused on what either of them ship on their client and server portfolios but perhaps more focused on instruction set parity/fragmentation.
Anyway it's too far off, we will see then

 

[511]

Have to factor the jump from Intel 3 to A14 and 14A would be big(density-wise)

The jump from Intel 3 to A14/14A is smaller than Intel's jump from 14nm to 10nm in area.

 

[regen1]

The jump from Intel 3 to A14/14A is smaller than Intel's jump from 14nm to 10nm

Still a very significant jump.
Cores should be more area-efficient going forward compared to present P-core designs.

 

[511]

Still a very significant jump.
Cores should be more area-efficient going forward compared to present P-core designs.

i was talking about Area the PnP characteristic should be a lot better

 

[DrMrLordX]

It's cool that the two rivals are working together to advance x86. Intel and AMD have adopted each other's new instructions in the past, but AFAIK they haven't worked together on new instructions. It's a unique situation, almost democratic.

So long as we don't get another FMA4-to-FMA3 situation, it might work out in everyone's favor.

 

[regen1]

Both Intel and AMD should have a successor to AMX already discussed in the committee.

AMD & Intel Mark x86 Ecosystem Advisory Group's Anniversary: FRED, ACE, AVX10, ChkTag - Phoronix

www.phoronix.com

In one year of the x86 Ecosystem Advisory Group, they are celebrating key technical milestones around Flexible Return Event Delivery (FRED) being finalized, AVX10 as the next iteration of Advanced Vector Extensions, ChkTag as a unified x86 memory tagging effort, and ACE as Advanced Matrix Extensions (AMX) for matrix multiplication.

ACE is what AMD and Intel is defining as the future of AMX for both vendors. AMD getting onboard with AVX10 remains exciting and was previously confirmed along with the FRED efforts.

ChkTag for x86 memory tagging is the main new joint initiative to talk about for AMD and Intel working together to fend off buffer overflows and use-after-free errors. The ChkTag specification is expected to be published later this year.

ChkTag: x86 Memory Safety

ChkTag: x86 Memory Safety Memory safety violations due to programming errors have long afflicted software. Industry and academia have been searching for solutions to this problem. As first noted in August 2025 posts by Intel and AMD x86 Ecosystem Advisory Group (EAG) leaders [1, 2], Intel and...

community.intel.com

 

[poke01]

AMD & Intel Mark x86 Ecosystem Advisory Group's Anniversary: FRED, ACE, AVX10, ChkTag - Phoronix

www.phoronix.com

ChkTag: x86 Memory Safety

ChkTag: x86 Memory Safety Memory safety violations due to programming errors have long afflicted software. Industry and academia have been searching for solutions to this problem. As first noted in August 2025 posts by Intel and AMD x86 Ecosystem Advisory Group (EAG) leaders [1, 2], Intel and...

community.intel.com

So basically x86 MTE

 

[regen1]

https://www.amd.com/en/blogs/2025/amd-and-intel-celebrate-first-anniversary-of-x86-ecosys.html

ACE (Advanced Matrix Extensions for Matrix Multiplication): Accepted and implemented across the stack, ACE standardizes matrix multiplication capabilities, enabling seamless developer experiences across devices ranging from laptops to data center servers.

Standardizing x86 features​

Key technical milestones, include:

• FRED (Flexible Return and Event Delivery): Finalized as a standard feature, FRED introduces a modernized interrupt model designed to reduce latency and improve system software reliability.
• AVX10: Established as the next-generation vector and general-purpose instruction set extension, AVX10 boosts throughput while ensuring portability across client, workstation, and server CPUs.
• ChkTag: x86 Memory Tagging: To combat longstanding memory safety vulnerabilities such as buffer overflows and use-after-free errors, the EAG introduced ChkTag, a unified memory tagging specification. ChkTag adds hardware instructions to detect violations, helping secure applications1, operating systems, hypervisors, and firmware. With compiler and tooling support, developers gain fine-grained control without compromising performance. Notably, ChkTag-enabled software remains compatible with processors lacking hardware support, simplifying deployment and complementing existing security features like shadow stack and confidential computing. The full ChkTag specification is expected later this year – and for further feature details, please visit the ChkTag Blog.
• ACE (Advanced Matrix Extensions for Matrix Multiplication): Accepted and implemented across the stack, ACE standardizes matrix multiplication capabilities, enabling seamless developer experiences across devices ranging from laptops to data center servers.

 

[João Bortolace]

https://www.amd.com/en/blogs/2025/amd-and-intel-celebrate-first-anniversary-of-x86-ecosys.html

Not apx?

 

[regen1]

Not apx?

Excerpt from posts(same article) by Jeff McVeigh(Intel) and Robert Hormuth(AMD) in August this year, mentions APX.

Early wins to build on – and more to share in the coming days…

• FRED (Flexible Return and Event Delivery) – a modernized interrupt model that cuts latency and improves systems software reliability.
• AVX10 & APX – next generation vector and general purpose instruction set extensions that boost throughput while keeping code portable across client, workstation and server CPUs.

Spoiler: August Posts on x86 EAG

AMD, Intel, and partners collaborate on x86 computing | Jeff McVeigh posted on the topic | LinkedIn

Since its inception, the x86 Ecosystem Advisory Group (EAG) has been a driving force in shaping the future of x86 computing. Fueled by a deep â and somewhat unexpected â collaboration between AMD, Intel, and key industry partners, the group has made remarkable strides in aligning on...

www.linkedin.com

Advancing x86, Together

Advancing x86, Together Since its inception, the x86 Ecosystem Advisory Group (EAG) has been a driving force in shaping the future of x86 computing. Fueled by a deep – and somewhat unexpected – collaboration between AMD, Intel, and key industry partners, the group has made remarkable strides in alig

www.linkedin.com

 

[soresu]

Not apx?

AFAICT APX has simply been assimilated into AVX10, likely to simplify language and present it as a more ISA wide upgrade over AVX512.

If you look at the language used in the older August release and the new release it is almost identical with the sole exception of actually using the name APX.

Before it started with AVX10 and APX, now it just says AVX10.

 

[soresu]

I think that they changed the AMX name to ACE to avoid confusion with Apple's matrix core by the same name now rolling as an SME co processor instead.

 

[soresu]

So long as we don't get another FMA4-to-FMA3 situation, it might work out in everyone's favor.

Yes this is to me a thing far too long in the making.

Sadly though I fear that if Intel weren't in such dire straits that they would have continued doing what they want without any collaboration with AMD.

We'll just have to see whether this continues or evaporates once Intel gets a bit of fair weather success under their belts again.

 

[adroc_thurston]

AFAICT APX has simply been assimilated into AVX10

no?
They're very very very very different things lmao

 

[soresu]

no?
They're very very very very different things lmao

Check out the language between the 2 information releases.

• AVX10 & APX – next generation vector and general purpose instruction set extensions that boost throughput while keeping code portable across client, workstation and server CPUs.

• AVX10: Established as the next-generation vector and general-purpose instruction set extension, AVX10 boosts throughput while ensuring portability across client, workstation, and server CPUs.

Use of the term APX aside the text is virtually identical and they were grouped together in the older August release regardless of how functionally separate they are.

 

[adroc_thurston]

Use of the term APX aside the text is virtually identical and they were grouped together in the older August release regardless of how functionally separate they are.

https://twitter.com/x/status/1978134012968263737

 

[soresu]

https://twitter.com/x/status/1978134012968263737

 

[soresu]

If this is from a presentation then perhaps they need to tell the PR team responsible for the AMD blog.

 

[regen1]

I think that they changed the AMX name to ACE to avoid confusion with Apple's matrix core by the same name now rolling as an SME co processor instead.

It's not just naming convention, it(ACE) is different from what Intel's AMX has been(already mentioned in an earlier post, linked below).

Even before the formation of x86 advisory committee AMD was working on AMX.
Both Intel and AMD should have a successor to AMX already discussed in the committee.
Don't know whether it will be exact same implementation or somewhat different on both sides, also if it would be named the same. The successor should come to both client and server.

This is an AMD slide at OCP2025:

 

[soresu]

This is an AMD slide at OCP2025:View attachment 132063

Any idea why ChkTag and ACE are in quotation marks?

 

[regen1]

Any idea why ChkTag and ACE are in quotation marks?

May be someone at AMD can answer that.
Perhaps it is because rest are (kinda) acronyms("ChkTag" can't be and "ACE" is still expanded to/referred as Advanced Matrix Extensions)