Intel ''64'' finally

[Alkaline5]

Originally posted by: DAPUNISHER

Originally posted by: AWhackWhiteBoy

it is already known that AMDs current architecture doesn't need more bandwidth.

we'll see what happens with two cores on one die fighting for the memeory bandwidth

It hasn't crippled dual Opteron setups why should it cripple dual core?

Currently each Opteron gets its own dedicated memory bank. IMO that's an unlikely feature for the SOHO market, so Whack has a point.

 

[DAPUNISHER]

Originally posted by: Alkaline5

Originally posted by: DAPUNISHER

Originally posted by: AWhackWhiteBoy

it is already known that AMDs current architecture doesn't need more bandwidth.

we'll see what happens with two cores on one die fighting for the memeory bandwidth

It hasn't crippled dual Opteron setups why should it cripple dual core?

Currently each Opteron gets its own dedicated memory bank. IMO that's an unlikely feature for the SOHO market, so Whack has a point.

I thought I read that in some dual opteron setups that the 2nd CPU has to address memory through a tunnel to the first, is that false?

 

[AWhackWhiteBoy]

Originally posted by: DAPUNISHER
It hasn't crippled dual Opteron setups why should it cripple dual core?

dual opteron = two memory controllers, double the bandwidth

 

[AWhackWhiteBoy]

Originally posted by: DAPUNISHER

I thought I read that in some dual opteron setups that the 2nd CPU has to address memory through a tunnel to the first, is that false?

thats the case on cheaper chipsets. many of the cheap MSI/Gigabyte athlon MP motherboards were like this, hence the cheap price.

edit: obviously for MPs is was definatly different though. the 2nd MP would have to address memory ALREADY addressed by the primary processor.

 

[Alkaline5]

Originally posted by: DAPUNISHER

Originally posted by: Alkaline5
Currently each Opteron gets its own dedicated memory bank. IMO that's an unlikely feature for the SOHO market, so Whack has a point.

I thought I read that in some dual opteron setups that the 2nd CPU has to address memory through a tunnel to the first, is that false?

That's true. Opteron's have that ability, but it's not the ideal situation. I haven't come across any benches on that, but it could be an interesting forecast for future dual-core A64s.

 

[DAPUNISHER]

Originally posted by: AWhackWhiteBoy

Originally posted by: DAPUNISHER
It hasn't crippled dual Opteron setups why should it cripple dual core?

dual opteron = two memory controllers, double the bandwidth

So why can't each core have it's own controller to access memory independently?

 

[AWhackWhiteBoy]

Originally posted by: DAPUNISHER

So why can't each core have it's own controller to access memory independently?

Not sure, although it would kill off the FX line. dual core, dual channel? a mandatory 4 sticks of ram per PC!

 

[DAPUNISHER]

Originally posted by: AWhackWhiteBoy

Originally posted by: DAPUNISHER

So why can't each core have it's own controller to access memory independently?

Not sure, although it would kill off the FX line. dual core, dual channel? a mandatory 4 sticks of ram per PC!

How the heck do you arrive at needing 4 sticks? No one makes you use dual channel and for AMD it does very little anyways, even on nF2 so WTF? The question I'm asking is do independent controllers for each core regardless of wether they are single or dual, solve the bandwidth problem? It certainly seems like it would.

 

[AWhackWhiteBoy]

when you add multiple memory controllers the efficency of the ram overall decreases. if you add another memory controller the gains usually get slashed by a percentage, its not a linear increase in performance. on top of that the lack of dual channel will be another minor performance hit.

there are a few stories that AMD64 and opteron will start moving to DDR2 very late this year, but there hasn't been any confirmation from AMD on this yet.

 

[clarkey01]

"F is approporaite nomenclature since it's based on the failure that is prescott."

LMAO


amd for life

 

[VirtualLarry]

Originally posted by: RaynorWolfcastle

Originally posted by: DAPUNISHER
Unless they move the memory controller on-die they will still be getting their a$$ handed to them I suspect.

I read a while ago that Intel had a different solution to that problem. They wanted to put a high speed buffer/interface on RAM sticks. The result is that you could use any memory architecture behind the buffer and the motherboard would be none the wiser. Basically, you'd be decoupling the memory from the rest of the system; that would allow more flexibility for memory and since the buffer is basically a cache chip, the latencies would be much lower for many cases. I'll see if I can find the article.

I saw that too, FB-DRAM maybe? It was supposed to help with memory upgrading, decoupling the type of DRAM used. Kind of like moving the memory-controller onto the DIMM itself, and using a fast link from the chipset (pci-E, HT, etc?) to the "hub" when the DIMMs plugged in.

I don't know if it decreased latencies; if anything, I think that it actually increased them, but allowed for increasing the total number of DIMMs in the system without that number adversely affecting the latency even further. (Much like "registered ECC" DIMMs today.) It basically seemed like a server technology, for server installations that might "live" for a long time, long enough that DRAM technologies had moved forward a generation or two, and it increased the memory stability for really large DRAM arrays.

For the consumer segment, I can't ever see that technology taking off. It would add too much of the cost, for what, in the end-result in most OEM-built systems, is a "disposable" computer. You don't put expensive, long-lasting tech into disposable systems.

If I ever invested into a big multi-CPU server-type system, I might be interested in that FB-DIMM technology though, it did sound rather neat.

 

[VirtualLarry]

Originally posted by: DAPUNISHER

Originally posted by: AWhackWhiteBoy

Originally posted by: DAPUNISHER
It hasn't crippled dual Opteron setups why should it cripple dual core?

dual opteron = two memory controllers, double the bandwidth

So why can't each core have it's own controller to access memory independently?

That's a neat idea, I hadn't really considered that, but I suspect that AMD will implement a very high-speed internal crossbar/arbiter between the two CPU cores and the on-die memory controller, which itself could be single- or dual-channel. That would basically allow the best of both worlds, and still allow multi-chip SMP configs to access other CPU package's memory-controller and DRAM array via the magic of the HT links and the NUMA SMP Opteron memory design.

 

[caz67]

LOL..What about P64????

 

[iwantanewcomputer]

i'm pretty sure the reviews of dual core opty's i've seen had close up chip images showing 2 memory controllers and i think they each access separatememory banks

 

[DAPUNISHER]

Originally posted by: iwantanewcomputer
i'm pretty sure the reviews of dual core opty's i've seen had close up chip images showing 2 memory controllers and i think they each access separatememory banks

Linkage? TIA.

 

[Zebo]

Anyone know what ED means by this:

"The Opteron infrastructure has a number of decided advantages over the Xeon infrastructure: higher FSBs, how much and in what way memory is addressed, integrated memory controller, hypertransport between the CPUs. The first can be quickly addressed by Intel, the second can be addressed in a while, the others can't.

It's really the non-64-bit features that make Opteron formidable against Xeon, especially in multi-processor systems.

Even in 64-bit-dom, the issue isn't how much memory each can address. Outside of supercomputers, that's irrelevant. It's how the two address memory above 4Gb that really matters. Intel is using a kludgy, performance-hurting, form of protected mode, while AMD doesn't. That's the critical difference, not total memory addressing. "


http://www.overclockers.com/tips00636/