Yep. Pin count difference comes from the reduced need for power-pins with the reduced power-consumption profile of the low-TDP parts combined with the (likely) reduced channel-width for memory I/O.
BTW I didn't make that statement out of some special prognostication skillz...I was basically doing the Captain Obvious thing by using the fact that this is exactly what both Intel and AMD do with their current mobile/laptop CPU's (mobile chips are desktop die put thru extra validation and binning, as ilkhan expanded on)...I merely extended the status quo to include the next generation parts from Intel.
I was unaware of both the mobile/desktop chip link and the ability to put the same chip in a different pin package.
How do you differentiate between validation and binning? Binning I understand, not validation.
On mobile parts there are additional power states which are validated as functional and operating to spec whereas in the desktop chip they are simply disabled by microcode regardless whether they could work or not.
DTS (the on-die digital temp sensor) is another difference handled in validation. For mobile chips the DTS is validated for TJmax purposes while the desktop chips aren't as rigorously calibrated and validated for functionality (accuracy/precision).
There was a CPU review on the AT site months ago that spent some time talking about this; I briefly looked but I can't figure out which one it was.
edit: This article details the powerstates, although this one provides a much cleaner cliff's notes overview and the following example:
Validation MUST happen for every chip on the wafer, regardless of mobile or desktop. It must simply work, no point otherwise. The minor extra validation related to mobile C states can be thought of as additional binning criteria.
In the unlikely event that a chip fails a mobile C state validation, then that chip could be binned to a desktop chip if all else works.
I was trying to make a simple concept difficult. Thanks for the linked articles.
So in your mind the extra validation that goes into XEON and Opteron chips which differentiates them from their otherwise identical desktop bethren is...just binning?
That went over my head. I have zero knowledge about servers, except that somehow you can put more than one CPU on a MB.
I'm not looking for a fight, quite the contrary, I'm very appreciative of all the knowledge you've shared. My summary was simply an attempt to state things in my context.
So far we've only talked desktop and mobile, but if you want to lay more on me, I'm listening.
No no, nothing confrontational of the sort is happening here. My laziness at the keyboard resulted in a terse post that I can see in retrospect could be read as a rebuttal to your post (which wasn't the intent) versus an example of the Socratic method of teaching that I generally strive to employ in my efforts to help people.
I was giving you yet another example of where the terminology of "validation" is used to differentiate the functionality of a chip, in this case the server chips, if it doesn't pass validation then it gets shunted down the totem pole to desktop SKU market.
Same as happens with the mobile chips, if a C-state circuit doesn't function to spec (doesn't pass validation) including the DTS then they most certainly get shipped as desktop chips provided the chip still validates as functional in all the right areas and bins out as needed to match an existing sellable SKU.
Take 45nm penryn for example, see this slide, all these parts on this slide come from the exact same die printed on the wafers. On the wafer, what will eventually be a mobile chip could quite literally be sitting next to what will become a server chip could be sitting next to what will become a desktop chip.
The differences in where chips are headed in the marketplace once liberated from the wafer all come down to validation and binning.
There are a few special cases where this is not true, most recently for Intel's quad-socket x86 platforms they use special XEON chips that are not cut from the same wafer as the others. Dunnington for example, a 6core penryn-type chip. And the upcoming Nehalem EX (aka Beckton), an 8core nehalem-type chip.
Would you not agree that few chips fail second order validation checks? If the chip works at all, suitable for a desktop, then very few fail the second order criteria, C states, server criteria, etc.
I'm simply suggesting that once primary validation is obtained, it works. Then speed and voltage binning are the primary factors which determine which bucket, (server, mobile or desktop) the die goes into. While I understand the secondary validation criteria and the test only takes a few mill-seconds, their are few failures after the primary test.
If you disagree, say so, and I'll go with your position. You clearly know more than I on this subject, Yoda.
This amazes me. How is this unique functionality activated? Micro-code or laser scribe or ???
LokutusofBorg
Golden Member
- Mar 20, 2001
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I've wondered about this (validation and binning) from a different angle. When a new CPU is announced (like the Q9650) those dies are coming off the same wafers that 9550s and probably Q8x00s etc are coming from, right? And since the 9650 is rarer, they probably only started getting cores workable as a 9650 once they'd made some changes to the process, fixed some things, started getting higher yields. Or maybe not, but they were rare enough that they had to stockpile them for a while before they could offer them to market. Cause saying "we have a Q9650, but we only have 10 of them we can sell" just doesn't fly. They have to wait until they have some inventory threshold before they can offer them for sale as an official part. And even then, if 9550s are selling better, and they don't have the inventory, then some dies rated for 9650 may be sold as 9550s to meet the demand.
With so many things to care/worry about in this world, it's weird that this sort of thing is so interesting to me.
With so many things to care/worry about in this world, it's weird that this sort of thing is so interesting to me.
ilkhan
Golden Member
- Jul 21, 2006
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Of course. Why do you think some chips overclock so well? While the margins on higher end parts per chip are better, not everybody will pay for the speed. Thus lower clocked chips are created to fill the market. Just because a part can be binned at 3Ghz doesn't mean it's going to end up at the market at 3Ghz.
The exact sequence of validation, binning, etc depends on each company and even more so to the specific product in question. It is all optimized to reduce tester time and increase the efficiency of the whole process. Generic terms like "validation" and "binning" lose meaning once you delve into that level of the details regarding sequencing.
Suffice to say what you outline above is plausible, at the level of detail we are capturing here there is nothing in your sequence that would invalidate it as a viable iterative validate/bin sequence.
Both. Some features are deactivated by explicit microcode, some are activated by explicit microcode, some are fused off permanently (they hope).
"Laser scribe" is the process by which the lot number and wafer number is inscribed onto each wafer as it begins its journey thru the fab. I am assuming you were thinking "fuse laser-cut" or something along those lines when you used that term.
Fusing use to be done by way of focusing a laser on regions of metal in the die to intentionally overheat the metal in a catastrophic failure manner causing the circuit to then become an electrical open. This method of "fusing off" certain areas of the chip has been replaced with actual electrical fuses in the sense of the phrase in which certain parts of the chip (the fuse) is over-volted in such a way that the flow of current combined with Joule heating (ohms law) overheats the metal line in the fuse causing it to melt in a catastrophic manner resulting in an electrically open circuit.
Fusing is done for most of your typical "chip harvesting" yield enhancement techniques. Sram redundancy, core segmentation, etc.
http://www.patentstorm.us/pate...61330/description.html
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
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I read that the mainstream Nehalem will have higher bCLK and have a lower multiplier. It's very likely the QPI bus will be higher for Westmere parts because the QPI bus speed is going from 6.4GT/s to 8.5GT/s for 32nm. Though whether that translates to bCLK is a different story.
I can't think of any performance-related reasons whatsoever for Intel to increase bclk.
Are there any?
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