That is when code doesn't use AVX256 and memory pressure is low.
It's an average across many tests, including with AVX256. Overall, Gracemont is slightly better in int, slightly worse in FP.
Then why haven't they?
Yes, of course, they improve the basic logical design of and add additional resources to the core, then they perform the needed additions to make sure that HT can still take advantage of those new and expanded features. They are getting 3-5% while also devoting additional resources to HT. What we are proposing is to, instead of allocating additional resources to HT, instead, spend them on making the ST performance of the core better. That way, the generational improvement would be MORE THAN the 3-5% per generation.
E-Cores doesn't have native AVX256 units, it is like Zen1. Also we don't know how a Skylake ported to Intel 10nm+++/7 will perform or its size.
Well, it was not worth it for whatever reason: Too expensive, it would take too long, it would decrease performance in some aspect they did not want, it would interfere with some other function, it would increase complexity too much, it would bring some vulnerability, it would be awful and inconvenient, etc.
It's like how Zen 4 handles AVX-512, but you don't see people complaining about that, do you? It clearly works well enough in practice. The benchmarks speak for themselves.
This happens because you start both instances with the same priority so task manager assigns the same amount of resources to each.Needless to say how shocking this is to me, to realize, that I got something as fundamental as SMT wrong for more than 2 decades - after having spent countless hours of learning about technical aspects of CPUs. Somehow the assumption was burned into my brain, that the second thread only gets the resources that the prime one does not use - and that is also how Intel was explaining it in Layman's terms, when they introduced it. Also, most articles only mention the total benefit of SMT but do not go into detail if the throughput of these two threads is symmetrical or not.
But the positive take-away for me is that I learned (and proved) something fundamental today. Thanks for bringing me on that path
But you are assuming that this is possible without any basis in reality without having any facts. You just believe it so it must be true. You can't possibly know if the IPC improvement they have each gen isn't the max that is possible, no matter what they do.
What would lead you to believe that it doesn't?
Even if they did nothing else than just use the freed space to make caches larger, this elementary move would help performance. And there are many improvements they can make by just adding more already existing functional units. And by making things simpler they can easier implement new ways of how things work.
The fact that we're still getting IPC improvement...? And that higher IPC archs exist on the market today?
Would be helpful if you tell us HOW they could make things simpler. From an engineering point of view. With details about the actual execution units and what needs to be changed/enhanced in those units. What you are doing is wishful thinking. Your thoughts are perpendicular to the reality plane.
Nah, Skylake's IPC gain was actually very modest. Anandtech only found +5.7% vs Haswell, and that's ignoring Broadwell. Other sites had somewhat better results with better memory (DDR4), but nothing even close to 40%.
Golden Cove had about a 20% IPC gain over Rocket Lake, and if I recall the gain over Skylake was over 40%, all without sacrificing SMT.
AMD once published a good diagram about how SMT resource allocation works.
That's the thing Kocicak is not understanding. With so much work already done and SMT implementations quite matured, who of these two x86 behemoths would throw away their years of hard work out the window, just like that, in a world that's moving to multicore workloads more and more? They would only do that if SMT somehow becomes an impediment to higher speeds. But as Carfax83 pointed out, SMT reduces the impact of branch mispredictions that increase with higher speeds. The only way they would leave SMT out is if they redesigned everything from scratch. So maybe (BIG maybe) Lunar/Nova Lake may not have SMT. But with the way these two companies are obsessed with CBR23 scores, I see SMT4 and SMT8 as more likely.
I think that we should ignore Kocicak. First he says that CPU that take over 100 watts should be outlawed, then buys a 13900k, then a ..... (a bunch of different CPUs and returns them) I can't take this kind of user seriously. We all know SMT works most of the time to our advantage, lets just ignore this guy.
That's the sunk cost fallacy. The question is whether the incremental effort needed to maintain/update SMT is worth having the feature at all. The world is moving to multicore workloads, but those are being shifted to different cores altogether. Like, disabling SMT on Haswell made a huge difference. On Raptor Lake? Meh.
That's precisely the argument. Or rather, that implementing SMT is inherently trading off some amount of IPC/single thread performance.
That's not really how it works. It can gain more throughput by keeping the core busy while a thread is waiting, but does nothing for single thread performance. The opposite, really.
That, I'd agree with. So on the Intel side, either Lion Cove, or if not that, then Royal. AMD, tougher to say. Maybe Zen 6 or 7.
Nah, Skylake's IPC gain was actually very modest. Anandtech only found +5.7% vs Haswell, and that's ignoring Broadwell. Other sites had somewhat better results with better memory (DDR4), but nothing even close to 40%.
The Intel 6th Gen Skylake Review: Core i7-6700K and i5-6600K Tested
www.anandtech.com
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