Discussion Intel’s Unified Core: There is hope

[511]

But crestmont is only 20% the area of a RWC core.
Sure you might be feeding it less power, but the core is also way, way more dense.
But also consider this, a P-core on N2 will likely also already be smaller than that same core on 18A-P because of N2's better density, so in that sense the N2 core could also have higher thermal density, right?

You can't say about core density without having access to SEM images or teardowns or if Intel provides the info.

Thermal density is a problem that has been a thing for years and years and years, and companies always find a way to mitigate it time and time again. And yet BSPD apparently is the one problem they can't solve though?
The worst part about all of this though, is that 18A-P was always claimed to be a performance focused node. Both by analysts and Intel themselves. So if 18A-P doesn't have any performance advantage, due to thermal issues from BSPD, what exactly does it haven then?

This time the transistor is sandwiched between Power and Signal wires not the fact that xtor is making direct contact with the cooler.

So Intel is willing to pay for it for Wildcat Lake, a low end, high volume product, but not for NVL-S compute tiles.
Intel is willing to pay for it for the IO die of NVL but not the compute tiles.
Intel is willing to pay for it for the iGPU tiles, but not the compute tiles.
If Intel had to decide what tiles they want to fab on 18A because they couldn't pay for the capacity they wanted, so many other tiles could have been easily shifted around to make room for NVL-S compute tiles being internal, which would obviously save them more money than the alternative.
And yet they didn't.

only 2 Desktop tile is on N2(8+16 and one with bLLC) it doesn't mean 18AP is bad.
If 18AP is bad than why don't they use N2 for their mobile line up why is 4+8/4+0 tile on 18AP for NVL if anything Mobile is their main volume driver

 

[Io Magnesso]

Intel 18ap Performance of Intel 18AP is decreasing

But crestmont is only 20% the area of a RWC core.
Sure you might be feeding it less power, but the core is also way, way more dense.
But also consider this, a P-core on N2 will likely also already be smaller than that same core on 18A-P because of N2's better density, so in that sense the N2 core could also have higher thermal density, right?
Thermal density is a problem that has been a thing for years and years and years, and companies always find a way to mitigate it time and time again. And yet BSPD apparently is the one problem they can't solve though?
The worst part about all of this though, is that 18A-P was always claimed to be a performance focused node. Both by analysts and Intel themselves. So if 18A-P doesn't have any performance advantage, due to thermal issues from BSPD, what exactly does it haven then?

So Intel is willing to pay for it for Wildcat Lake, a low end, high volume product, but not for NVL-S compute tiles.
Intel is willing to pay for it for the IO die of NVL but not the compute tiles.
Intel is willing to pay for it for the iGPU tiles, but not the compute tiles.
If Intel had to decide what tiles they want to fab on 18A because they couldn't pay for the capacity they wanted, so many other tiles could have been easily shifted around to make room for NVL-S compute tiles being internal, which would obviously save them more money than the alternative.
And yet they didn't.

 

[Io Magnesso]

It's supposed to be a tock core. Problem is that the leaked NVL ST perf slide is horrendous, so IPC uplift might honestly be on par with LNC or even less, not GLC or SNC level.
I doubt it's nothing to negative gains. Negative gains especially make no sense....
Realistically, I doubt Zen 6 vs Panther Cove has any sort of real IPC gap.
The question in server would be how bad the all core boost frequency difference will be, considering the node gap + architectural weakness from Intel.
And ig also how the vectorized perf would be.

It's a minus gain
Performance will definitely decrease

 

[Io Magnesso]

T Adopting the TSMC N2 will not solve the problem.
It's a waste of sand

No, those mitigations were BSPD specific.
BSPD undoubtedly causes thermal hotspot issues, sure. But tbf you don't even have to benefit from the higher cell utilization (higher density, more thermal hotspot issues) either.

Yes, so when they go N2, they know it's better.

Neither time or volume are factors. NVL desktop is launching 2H 2026, there's no way 18A or 18A-P isn't ready by then.
Volume isn't a factor either, Intel claims they can greatly expand capacity in their EUV fabs if customers ask for it- they already built out all they want/need for internal, and could build out even more if they want to.

 

[Io Magnesso]

If the translation is actually decent, it says that Diamond Rapids using Lion Cove variant will close the gap, but overall Xeon 7 is "not good". Looks like they'll bleed server share at least until Xeon 8.

Talks about politics how the P core team was able to get all high performance projects until Skymont exceeded expectations. I read somewhere how some Intellers hated Skymont because of how well it did. Talk about politics! It's supposed to be one company!

Regardless of claims of technical superiority, in the end it's all down to people and relationships. Supposedly some of the smartest group of people in the world acting like children.

I doubt Unified Core is "unified" as they claim. It'll likely be more akin to how Core 2 "unified" Pentium M and Netburst. Other than the quad pumped bus and good vector performance, there was not much of Netburst in Conroe/Merom.

Most of P core ideals are likely going to die with "Unified Core". Not gonna miss any parts of the P core team. In their best days(Pentium M, Conroe, Sandy Bridge) IMO they did worse than the E core one.

Skumont is good, but since it's Intel after all, the young E Core design team is incompetent
Their luck ran out.
Well, even if I join another company, I think I'll be fired soon because I'm incompetent. lol

 

[Io Magnesso]

Skumont is good, but since it's Intel after all, the young E Core design team is incompetent
Their luck ran out.
Well, even if I join another company, I think I'll be fired soon because I'm incompetent. lol

Let's support the ARM IP core, which is said to be better than Apple's core, rather than saying that. lol ARM's IP core that you say is excellent
Well, the ARM IP core hasn't beat Apple yet.
Well, the gap is getting smaller, though lol

 

[poke01]

Let's support the ARM IP core, which is said to be better than Apple's core, rather than saying that. lol ARM's IP core that you say is excellent
Well, the ARM IP core hasn't beat Apple yet.
Well, the gap is getting smaller, though lol

We can’t give up hope till unified core

 

[Geddagod]

You can't say about core density without having access to SEM images or teardowns or if Intel provides the info.

I find it hard to believe that you can't believe an E-core is more dense than a P-core lol.
Why do you think a P-core is more dense than an E-core, I'm curious?

This time the transistor is sandwiched between Power and Signal wires not the fact that xtor is making direct contact with the cooler.

Which both TSMC and Intel have researched for, and have mitigations for.
But also, didn't address this question:
The worst part about all of this though, is that 18A-P was always claimed to be a performance focused node. Both by analysts and Intel themselves. So if 18A-P doesn't have any performance advantage, due to thermal issues from BSPD, what exactly does it haven then?
Not for desktop, because apparently Fmax at those voltages suffer. Not for phone chips or server, where low power perf matters the most. Not for GPUs, where density is important. At best it only helps in laptop chips, but even then, laptops don't clock that much lower than desktop chips...

edit: just want to point out, TSMC outright says on their A16 slide that the node is targeted for HPC products with complex signal routes and dense power delivery network

If let's say you are right, and there is a Fmax regression where laptop chips can be fabbed on 18A-P but desktop chips can't, is Intel really going to waste all this money going external for a ~5% difference in Fmax?

only 2 Desktop tile is on N2(8+16 and one with bLLC) it doesn't mean 18AP is bad.

It means that Intel thinks 18A-P is not competitive with N2. Very likely they think the difference is a full node behind. Otherwise, they likely would have stuck by their internal node.

f 18AP is bad than why don't they use N2 for their mobile line up why is 4+8/4+0 tile on 18AP for NVL if anything Mobile is their main volume driver

The fact that 18A-P is used in lower power applications where N2 is used in the higher voltage stuff should be a key indicator that this wasn't not a engineering decision lol.
They have to keep a good amount of volume on 18A, otherwise the economics of the node, as well as Intel's margins, start crumbling down.
This was a financial difference.

 

[Io Magnesso]

I find it hard to believe that you can't believe an E-core is more dense than a P-core lol.
Why do you think a P-core is more dense than an E-core, I'm curious?

Which both TSMC and Intel have researched for, and have mitigations for.
But also, didn't address this question:
The worst part about all of this though, is that 18A-P was always claimed to be a performance focused node. Both by analysts and Intel themselves. So if 18A-P doesn't have any performance advantage, due to thermal issues from BSPD, what exactly does it haven then?
Not for desktop, because apparently Fmax at those voltages suffer. Not for phone chips or server, where low power perf matters the most. Not for GPUs, where density is important. At best it only helps in laptop chips, but even then, laptops don't clock that much lower than desktop chips...

If let's say you are right, and there is a Fmax regression where laptop chips can be fabbed on 18A-P but desktop chips can't, is Intel really going to waste all this money going external for a ~5% difference in Fmax?

It means that Intel thinks 18A-P is not competitive with N2. Very likely they think the difference is a full node behind. Otherwise, they likely would have stuck by their internal node.

The fact that 18A-P is used in lower power applications where N2 is used in the higher voltage stuff should be a key indicator that this wasn't not a engineering decision lol.
They have to keep a good amount of volume on 18A, otherwise the economics of the node, as well as Intel's margins, start crumbling down.
This was a financial difference.

Intel 18AP's purposeful IP and ease of handling improvements
There are some performance improvements as well. The main focus is to improve the base 18A and expand the application.
This may not be as good as the TSMC process, but it can also be used for mobile applications.

By the way, I don't think Intel 18A(P) will be abandoned.
Even after the Intel 14A comes out, I think it will be available as an option for customers.
Whether it's actually used by the customer is another matter.

 

[Io Magnesso]

I find it hard to believe that you can't believe an E-core is more dense than a P-core lol.
Why do you think a P-core is more dense than an E-core, I'm curious?

Which both TSMC and Intel have researched for, and have mitigations for.
But also, didn't address this question:
The worst part about all of this though, is that 18A-P was always claimed to be a performance focused node. Both by analysts and Intel themselves. So if 18A-P doesn't have any performance advantage, due to thermal issues from BSPD, what exactly does it haven then?
Not for desktop, because apparently Fmax at those voltages suffer. Not for phone chips or server, where low power perf matters the most. Not for GPUs, where density is important. At best it only helps in laptop chips, but even then, laptops don't clock that much lower than desktop chips...

edit: just want to point out, TSMC outright says on their A16 slide that the node is targeted for HPC products with complex signal routes and dense power delivery network

If let's say you are right, and there is a Fmax regression where laptop chips can be fabbed on 18A-P but desktop chips can't, is Intel really going to waste all this money going external for a ~5% difference in Fmax?

It means that Intel thinks 18A-P is not competitive with N2. Very likely they think the difference is a full node behind. Otherwise, they likely would have stuck by their internal node.

The fact that 18A-P is used in lower power applications where N2 is used in the higher voltage stuff should be a key indicator that this wasn't not a engineering decision lol.
They have to keep a good amount of volume on 18A, otherwise the economics of the node, as well as Intel's margins, start crumbling down.
This was a financial difference.

No, Intel 18A is The original position is the 5nm generation process node at Intel.
This is two generations behind the state-of-the-art N2 node
To be honest, it's wonder that the 5nm generation process can compete with the 3nm generation process. It's incredibly strange

 

[511]

It's a minus gain
Performance will definitely decrease

proof?

I find it hard to believe that you can't believe an E-core is more dense than a P-core lol.
Why do you think a P-core is more dense than an E-core, I'm curious?

just cause it's an area efficient core doesn't mean it is denser than the P Core P core can be bad as well in density and traditionally Intel's P core has been worse.

Which both TSMC and Intel have researched for, and have mitigations for.
But also, didn't address this question:
The worst part about all of this though, is that 18A-P was always claimed to be a performance focused node. Both by analysts and Intel themselves. So if 18A-P doesn't have any performance advantage, due to thermal issues from BSPD, what exactly does it haven then?
Not for desktop, because apparently Fmax at those voltages suffer. Not for phone chips or server, where low power perf matters the most. Not for GPUs, where density is important. At best it only helps in laptop chips, but even then, laptops don't clock that much lower than desktop chips...

which analysts? there is no chip analysts with Intel Internal PDK i am not talking about the external PDK which is not comparable to the internal version.

edit: just want to point out, TSMC outright says on their A16 slide that the node is targeted for HPC products with complex signal routes and dense power delivery network

If let's say you are right, and there is a Fmax regression where laptop chips can be fabbed on 18A-P but desktop chips can't, is Intel really going to waste all this money going external for a ~5% difference in Fmax?

Laptop chips can't turbo 30W do deliver ST all the desktop chips are clocked outside of their efficiency window they just crank the clock cause they have thermal headroom

It means that Intel thinks 18A-P is not competitive with N2. Very likely they think the difference is a full node behind. Otherwise, they likely would have stuck by their internal node.

it's not a full node behind it's only behind in density.

The fact that 18A-P is used in lower power applications where N2 is used in the higher voltage stuff should be a key indicator that this wasn't not a engineering decision lol.

you are contradicting yourself here the reason they are using 18AP for low power application and N2 for HVT stuff means that 18AP isn't suitable for desktop it's such a clear engineering decision.

They have to keep a good amount of volume on 18A, otherwise the economics of the node, as well as Intel's margins, start crumbling down.
This was a financial difference.

well they have their product stack on Intel nodes for 2-3 year at least outside few specific tiles so they have that problem solved mostly.

 

[Io Magnesso]

proof?

just cause it's an area efficient core doesn't mean it is denser than the P Core P core can be bad as well in density and traditionally Intel's P core has been worse.

which analysts? there is no chip analysts with Intel Internal PDK i am not talking about the external PDK which is not comparable to the internal version.

Laptop chips can't turbo 30W do deliver ST all the desktop chips are clocked outside of their efficiency window they just crank the clock cause they have thermal headroom

it's not a full node behind it's only behind in density.

you are contradicting yourself here the reason they are using 18AP for low power application and N2 for HVT stuff means that 18AP isn't suitable for desktop it's such a clear engineering decision.

well they have their product stack on Intel nodes for 2-3 year at least outside few specific tiles so they have that problem solved mostly.

Evidence?
Can't you believe what I'm saying?
Stop messing around.

 

[511]

Evidence?
Can't you believe what I'm saying?

Nope when Intel themselves have shown +8% performance improvement for 18AP vs 18A.

 

[Io Magnesso]

Nope when Intel themselves have shown +8% performance improvement for 18AP vs 18A.

It's different
I'm talking about not Intel 18AP
It's about P Core from NOVA LAKE
Can't you understand the story? lol

 

[511]

It's different
I'm talking about not Intel 18AP
It's about P Core from NOVA LAKE
Can't you understand the story? lol

Oh my bad sometimes your sentences are a bit confusing.

 

[Io Magnesso]

If Intel is wrong, you who believe it is also wrong
Training is required
Well, this applies to all companies…
Ah! I have to give feedback on iOS26!
That is a terrible design that completely ignores accessibility! It's not really a compliment!
Why is there someone who affirms that?
You have to correct the idea of Apple's rotten design!
Well, this is just one example.

 

[Geddagod]

just cause it's an area efficient core doesn't mean it is denser than the P Core P core can be bad as well in density and traditionally Intel's P core has been worse.

If the Fmax and max voltages it uses are much less, that enables them to increase density dramatically higher. You have to start to significantly increase area to hit the very high end of possible Fmax like the P-cores are doing.

which analysts?

Techinsights. Both Scotten Jones and Daniel Nenni insist that 18A-P is the highest performance node.
But again, you aren't answering the rest of the question. What is 18A-P good for then??

Laptop chips can't turbo 30W do deliver ST all the desktop chips are clocked outside of their efficiency window they just crank the clock cause they have thermal headroom

And despite that -H Laptop chips still on ~5% slower in Fmax.
So if BSPD is such a large concern for Fmax, even -H series chips suddenly become out of the scope for 18A-P.

you are contradicting yourself here the reason they are using 18AP for low power application and N2 for HVT stuff means that 18AP isn't suitable for desktop it's such a clear engineering decision.

It's because those 8+16 desktop dies are the most important compute tiles in Intel, which is why they are being the ones being sent to be fabbed externally.
Intel nodes are notoriously bad at perf/watt at the lower end of the V/F curve. Again, 18A has always been touted by both Intel and anlaysts as a high performing node, not something that will excel at the low end of the V/F curve.
18A-P isn't suitable for desktop, sure, but 18A-P isn't as good as N2 anywhere else either. If anything, it is likely worse.
Using N2 instead of 18A-P for DMR would likely be as big if not outright better of a benefit than using N2 instead of 18A-P for NVL 8+16 tiles is.

well they have their product stack on Intel nodes for 2-3 year at least outside few specific tiles so they have that problem solved mostly.

And this is exactly why they are still using 18A for a bunch of volume. Not because it's close to N2, like you are saying. It's because they outright have to.

it's not a full node behind it's only behind in density.

If this was the case, they wouldn't be going external. There's no way around it.
Intel is going external because N2 is outright better, and they think they need it in their high margin CCG segment. They can't make everything N2, because that would kill IFS, but they are using it where the margins and competitive need for it make sense.
There's no timeline excuses, there's no volume excuses.

 

[511]

If the Fmax and max voltages it uses are much less, that enables them to increase density dramatically higher. You have to start to significantly increase area to hit the very high end of possible Fmax like the P-cores are doing.

I will believe when I see the teardown for Crestmont or Skymont Gracemont already had a teardown and GMT/GLC both used the 60CGP and 408CH

Techinsights. Both Scotten Jones and Daniel Nenni insist that 18A-P is the highest performance node.
But again, you aren't answering the rest of the question. What is 18A-P good for then??

Daniel nenni also said that 18A is between N3X and N2 and I am holding him into that cause his analysis is based on his talks with people with PDK.

And despite that -H Laptop chips still on ~5% slower in Fmax.
So if BSPD is such a large concern for Fmax, even -H series chips suddenly become out of the scope for 18A-P.

5.3 GHz vs 6+ Ghz that NVl Is going to get

 

[Geddagod]

I will believe when I see the teardown for Crestmont or Skymont Gracemont already had a teardown and GMT/GLC both used the 60CGP and 408CH

AMD dense cores use the exact same logic libraries (TSMC N5 HD) as their classic cores too. There's dramatically more levers for core density and area than just cell libraries.

Daniel nenni also said that 18A is between N3X and N2 and I am holding him into that cause his analysis is based on his talks with people with PDK.

And yet Intel themselves don't seem to think so when they moved NVL-S onto TSMC.
Going to TSMC is a major cost and is directly against what Intel wants to do to benefit from margin stacking, and yet they still feel the need to do so.
Major, major red flag.

 

[511]

It's because those 8+16 desktop dies are the most important compute tiles in Intel, which is why they are being the ones being sent to be fabbed externally.
Intel nodes are notoriously bad at perf/watt at the lower end of the V/F curve. Again, 18A has always been touted by both Intel and anlaysts as a high performing node, not something that will excel at the low end of the V/F curve.
18A-P isn't suitable for desktop, sure, but 18A-P isn't as good as N2 anywhere else either. If anything, it is likely worse.
Using N2 instead of 18A-P for DMR would likely be as big if not outright better of a benefit than using N2 instead of 18A-P for NVL 8+16 tiles is.

Nope that is not the most important die the most important things for Intel is the cheap stuff they make in terms of Revenue.

And this is exactly why they are still using 18A for a bunch of volume. Not because it's close to N2, like you are saying. It's because they outright have to.

If this was the case, they wouldn't be going external. There's no way around it.
Intel is going external because N2 is outright better, and they think they need it in their high margin CCG segment. They can't make everything N2, because that would kill IFS, but they are using it where the margins and competitive need for it make sense.
There's no timeline excuses, there's no volume excuses.

18AP is going to enter risk production later this year ain't no way have they will have volume for DMR and NVL at the same time it's going to be a similar to story to Intel 3 believe what you will I am done here cause we aren't going to agree.

 

[511]

AMD dense cores use the exact same logic libraries (TSMC N5 HD) as their classic cores too. There's dramatically more levers for core density and area than just cell libraries.

And yet Intel themselves don't seem to think so when they moved NVL-S onto TSMC.
Going to TSMC is a major cost and is directly against what Intel wants to do to benefit from margin stacking, and yet they still feel the need to do so.
Major, major red flag.

There ain't there is for clocks but not for Density Cell libraries are be all and end all(including Finflex). For clocks you can use more Metal layers but for denser design you have to make shorter cell with lower leakage and lower drive current.

They have 70%+ die plus packing for margin stacking with NVL.

 

[Geddagod]

5.3 GHz vs 6+ Ghz that NVl Is going to get

Oh that Fmax difference is significant, but that would be a Fmax regression from TSMC N3B ARL (which has its own bucket of problems) vs 18A-P NVL tiles. A terrible look, which I don't think is going to happen.
Also, I just want to add something....
The significance of the 4+8 18A-P mobile (-H) die is likely going to be dramatically less than it is today.

Look at Intel's vs AMD's mobile positioning. If Zen 6's mobile high end die, even for the thinner non -HX laptops, includes a 12 core Zen 6 CCD, not even counting all the cores on the IOD, an Intel NVL 4+8+4 setup is not going to be enough to compete with that. Intel will be forced to use the 8+16 tile in that segment to compete in nT perf, there's no way around that either.

Nope that is not the most important die the most important things for Intel is the cheap stuff they make in terms of Revenue.

But they can't go to TSMC for that, since margins will die.
They are going external for the high margin stuff.

18AP is going to enter risk production later this year ain't no way have they will have volume for DMR and NVL at the same time it's going to be a similar to story to Intel 3 believe what you will I am done here cause we aren't going to agree.

Except that Intel claims they can build out even more Intel 18A volume any time they want!
Sure, it might be expensive, but Intel 18A is not volume limited by the time NVL launches.
Why will the be fabbing low end products like Wildcat Lake on 18A if it's that volume limited.
Why would they be fabbing iGPU and SOC tiles on this node then, rather than compute tiles?
The whole volume limitation side of this argument never made sense.

 

[511]

Oh that Fmax difference is significant, but that would be a Fmax regression from TSMC N3B ARL (which has its own bucket of problems) vs 18A-P NVL tiles. A terrible look, which I don't think is going to happen.
Also, I just want to add something....

This is on comparison with ARL-H and NVL-S not 18AP I don't know any clock info for it. I picked the wrong comparison here lol my bad.

Look at Intel's vs AMD's mobile positioning. If Zen 6's mobile high end die, even for the thinner non -HX laptops, includes a 12 core Zen 6 CCD, not even counting all the cores on the IOD, an Intel NVL 4+8+4 setup is not going to be enough to compete with that. Intel will be forced to use the 8+16 tile in that segment to compete in nT perf, there's no way around that either.

They have HX for that

But they can't go to TSMC for that, since margins will die.
They are going external for the high margin stuff.

Where they can simply swallow the cost

Except that Intel claims they can build out even more Intel 18A volume any time they want!
Sure, it might be expensive, but Intel 18A is not volume limited by the time NVL launches.
Why will the be fabbing low end products like Wildcat Lake on 18A if it's that volume limited.
Why would they be fabbing iGPU and SOC tiles on this node then, rather than compute tiles?
The whole volume limitation side of this argument never made sense.

Who is going to sponsor them they don't have too much money left if they want to ramp quickly they need money they are just giving them the maximum flexibility in terms of operation and cost ramping a fab cost $$$ they don't have much money.
Wild cat is like 70mm2 at max lol with 2+4 config.

 

[Io Magnesso]

If the Fmax and max voltages it uses are much less, that enables them to increase density dramatically higher. You have to start to significantly increase area to hit the very high end of possible Fmax like the P-cores are doing.

Techinsights. Both Scotten Jones and Daniel Nenni insist that 18A-P is the highest performance node.
But again, you aren't answering the rest of the question. What is 18A-P good for then??

And despite that -H Laptop chips still on ~5% slower in Fmax.
So if BSPD is such a large concern for Fmax, even -H series chips suddenly become out of the scope for 18A-P.

It's because those 8+16 desktop dies are the most important compute tiles in Intel, which is why they are being the ones being sent to be fabbed externally.
Intel nodes are notoriously bad at perf/watt at the lower end of the V/F curve. Again, 18A has always been touted by both Intel and anlaysts as a high performing node, not something that will excel at the low end of the V/F curve.
18A-P isn't suitable for desktop, sure, but 18A-P isn't as good as N2 anywhere else either. If anything, it is likely worse.
Using N2 instead of 18A-P for DMR would likely be as big if not outright better of a benefit than using N2 instead of 18A-P for NVL 8+16 tiles is.

And this is exactly why they are still using 18A for a bunch of volume. Not because it's close to N2, like you are saying. It's because they outright have to.

If this was the case, they wouldn't be going external. There's no way around it.
Intel is going external because N2 is outright better, and they think they need it in their high margin CCG segment. They can't make everything N2, because that would kill IFS, but they are using it where the margins and competitive need for it make sense.
There's no timeline excuses, there's no volume excuses.

No N2 is clearly better

Intel 18A is a 5nm generation process
At this point, two generations are inferior

 

[Philste]

Problem is that the leaked NVL ST perf slide is horrendous, so IPC uplift might honestly be on par with LNC or even less, not GLC or SNC level.

You mean the 1.1×ST and 1.6×MT slide? That's still Panther Lake vs Lunar Lake and has nothing to do with NVL.

Immediately after the Leak came out there were many people saying that NVL is wrong and Computerbase also wrote that the data matches the information they have for Panther Lake.