Such as your lack of knowledge about RAS features and usage.
Xeons have gone as far as hot-swapping cards and memory, and ECC registers, the first two of which are only marginally useful
(why aren't you shutting the computer down for a few minutes?). What RAS features does Itanium have that cannot be replaced with redundancy, if not supporting legacy software?
Or that your think that x86/x64 compilers can get you out of one of the biggest problems with x86/x64.
What big problem is that? I never said I think x86 compilers can get us out of some problem. I said that in-order uarches (and ISAs, in IA64's case) need compilers to be able to compete with out-of-order, and sometimes are stuck not being able to, without an undue amount of human attention on specific code paths, and then the improvements only apply when the tested profile matches the current data flow. Both in-order and out-of-order can greatly benefit from compiler improvements.
I dont think you realize at all that IA64 doesnt need a realtime scheduler at all because its done at compiletime. Something you cant do with x86/x64. Thats also why we saw the Mitosis project. Basicly wasting cores on guessing the right instruction sequence outcome to boost singlethreaded performance.
At the cost of how much bandwidth and power? It didn't improve performance enough to make up for generation x86 CPU improvements (and, ironically, can help x86, too: now, you can add helper threads, using ICC, though like with Mitosis, the benefits aren't as much as they thought they'd be). You
do need hardware scheduling, because the compiler does not have enough knowledge,
without profiling (which has its own issues), about the data flow of the program, to always offer good baseline performance.
All those that run IA64, POWER or Sparc today dont care about x86/x64 being faster. Because x86/x64 cant lift the task at all. And in those segments you dont care about software or hardware cost.
Then they aren't competing with x86, and won't
(nothing wrong with Power, FI, unlike IA64, and certainly a PPC CPU could compete with x86 CPUs, but IBM just doesn't care to). IMO, if software and hardware cost don't matter, you are in a market long overdue for a correction.
Right now only 1 Xeon x86/x64 model even got MCA.

Even Intel
desktop CPUs have had MCA for well over a decade. MCA
R Is limited, specifically for the purpose of charging more, for the time being (which, for small niche markets that used to use Big RISC, I'm OK with).
Amdahls law was about people having blind faith in multithreaded. You sit with an issue already with serialcode you cant fix on x86/x64.
No, Amdahl's Law is about predicting parallel performance. Any given implementation of an algorithm will have nearly identical scaling results, limited by bandwidth and latency of the system. I don't need faith: I have reality. Not only do I have the reality in which multithreading does work, but so does everyone else. SPARC (T-series and Fujitsu's, specifically), Power, and Itanium, FI, rely even more on multithreading than desktops/notebooks and COTS servers, for good performance, and they have the bandwidth to keep all those threads fed.
x86/x64 is a dead wall. The only good thing about x64 is that you have to redo pointers from x86. Also why x64 ports are relatively rare. And why its easy to port from x64 to IA64 and others.
No, it's not a wall. It just keeps looking that way to people that wish it were. x86 wasn't going to be able to do superscalar execution. Everyone was going to get stuck at 1 IPC. x86 was too complex for effective OOOE. And so on, and so forth. It hasn't been perfect, sustained FP performance has generally lacked, and it can be lacking when sustained very high bandwidth/thread is needed, but even those faults are becoming less and less.
x86-64 ports are mostly rare because they aren't needed too often. If you don't need more registers, larger registers, or more RAM, there's no reason to do it, unless your IA32 executable is incompatible. For x86, where cost and compatibility matter, that's a fair compromise, to support a single binary.