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Discussion i7-5775C: the blast from the past - Effect of large L4 cache in high-refresh-rate gaming

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blckgrffn

Diamond Member
May 1, 2003
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In this case, this extra cache would be inside the IOD, right?
I mean, if AMD went that route it seems like the GloFo silicon would be cheap yet efficient enough for a significant IOD cache. Who cares if it was $50-$100 (retail) more and boosted TDP by 10W? If it really helped mask memory performance it could be a wash in a system build cost scenario. It seems like where it helps it helps quite a lot.
 

LightningZ71

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Mar 10, 2017
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Given that the 12 and 16 core chips can have 64MB of L3 combined, the L4 would need to be at least twice that amount to be effective as a strictly victim cache and 4x as much if it was also going to be doing pre-fetch buffering too. The IO die is already rather large as it is. Even with their improved 12nm procss, cramming 128-256 MB into it won't work from a die size point of view. I don't think that GloFo has the needed die stacking techniques to even stack it on the IO die.
 

moinmoin

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Jun 1, 2017
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Given that the 12 and 16 core chips can have 64MB of L3 combined, the L4 would need to be at least twice that amount to be effective as a strictly victim cache and 4x as much if it was also going to be doing pre-fetch buffering too. The IO die is already rather large as it is. Even with their improved 12nm procss, cramming 128-256 MB into it won't work from a die size point of view. I don't think that GloFo has the needed die stacking techniques to even stack it on the IO die.
Such a massive L4$ shouldn't be on the same die using the same node anyway considering IO logic scales poorly while cache scales really well. This would be a candidate for X3D stacking or whatever, using the best fitting nodes per layer.
 

IntelUser2000

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Oct 14, 2003
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Even Intel realized these problems and in Skylake gen moved from L4 cache with tags to "system side" L4 memory cache, but i don't think they had much success with those either.
Skylake had some success with the Iris Plus(not to be confused with the Iris Pro, which are -H parts and using 45W or more) parts and upselling them as the premium+ config in already very expensive clamshells and 2-in-1s.

They probably gave it up because Gen 11 GPU on Icelake was able to beat it while abandoning the eDRAM. Tigerlake ups the performance further and still no eDRAM.

It's way better performance/cost wise to put a single HBM2 stack in there anyway.
 
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IntelUser2000

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Oct 14, 2003
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It eats into thermals fairly heavily. It's also no friend to total package power budgets.
Thermals/power shouldn't be a problem. Its rated at 3W with the first generation eDRAM in the Haswell Iris Pro having 1W standby. The second generation(I forgot where it was first used, but Skylake definitely uses it) cuts that to a quarter or something so you no longer have to sacrifice battery life going for eDRAM.
 

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