2.2.1 Loadline Definitions (REQUIRED)
To maintain processor reliability and performance, platform DC voltage regulation and
transient-droop noise levels must always be contained within the Vccmin and Vccmax
loadline boundaries (known as the loadline window). Loadline compliance must be
ensured across component manufacturing tolerances, thermal variation, and age
degradation. Loadline boundaries are defined by the following equations in conjunction
with the VCC regulator design parameter values defined in Table 2-2. In these
equations, VID, RLL, and TOB are known. Plotting VCC while varying ICC from 0 A to
Iccmax establishes the Vccmax and Vccmin loadlines. Vccmax establishes the
maximum DC loadline boundary. Vccmin establishes the minimum AC and DC voltage
boundary. Short transient bursts above the Vccmax loadline are permitted; this
condition is defined in Section 1.3.7.
Table 2-1. Loadline Equations
Loadline Equation
Equation 5: Vccmax Loadline VCC = VID (RLL* ICC)
Equation 6: Vcctyp Loadline VCC = VID TOB - (RLL* ICC)
Equation 7: Vccmin loadline VCC = VID 2*TOB - (RLL* ICC)
Loadline recommendations are established to provide guidance for satisfying
processor loadline specifications, which are defined in processor datasheets. Loadline
requirements must be satisfied at all times and may require adjustment in the loadline
value. The processor loadlines are defined in the applicable processor datasheet.