"Hyperthreading" on Athlon64 X2?

[GRIdpOOL]

Hmmm...
It looks like we could be in for more surprises over the next few weeks. I was geared up for a Venice, but now I am anxious to see what is fact and what is fiction about the X2.

 

[ahock]

Isn't it that hyper threading is a proprietary technology of Intel? Are they allowed to copy this similar to SSE instructions?

 

[thanatos355]

they couldnt stop them from developing their own ht-esq design.

 

[GRIdpOOL]

It is included in the SSE3 instruction set, so I guess so.

 

[MBrown]

So the X2s have Hyperthreading? It seems like more people would have known of this if it had Hyperthreading. And think AMD would have said that it had put Hyperthreading into the X2. Also does this mean the Venice and SD have Hyperthreading?

 

[ahock]

I dont know if AMD is really keen on putting hyperthreading in Athlon. I read an interview done by C/Net to Fred Weber and he said that this technology will not be appropriate with the current Athlon chips.

 

[GRIdpOOL]

Originally posted by: MBrown
So the X2s have Hyperthreading? It seems like more people would have known of this if it had Hyperthreading. And think AMD would have said that it had put Hyperthreading into the X2. Also does this mean the Venice and SD have Hyperthreading?

Nobody knew they were being launched tomorrow, so there may have been several things not released. I am very surprised also. I guess I will believe it when I see it.

 

[MBrown]

Originally posted by: GRIdpOOL
It is included in the SSE3 instruction set, so I guess so.

I found this at Mike's Hardware. "Venice also features 11 new SSE3 instructions - 2 fewer than Intel's SSE3 implementation as the Hyperthreading MONITOR andMWAIT instructions are not implemented." I guess this answers my question too.

 

[GRIdpOOL]

Originally posted by: MBrown

Originally posted by: GRIdpOOL
It is included in the SSE3 instruction set, so I guess so.

I found this at Mike's Hardware. "Venice also features 11 new SSE3 instructions - 2 fewer than Intel's SSE3 implementation as the Hyperthreading MONITOR andMWAIT instructions are not implemented." I guess this answers my question too.

Yeah. That looks like it is in line with what we know about Venice and San Diego.

 

[mamisano]

Did anyone actually read the article? All it means is that the Dual Athlon will enable the Hyperthreading bit on the chip. This way, when a program written with Hyperthreading support is run, it can take advantage of the 2nd core. It does NOT mean that AMD has included hyperthreading, they just want to take advantage of programs already designed for multithreading via Hyperthreading.

 

[ahock]

yes but from the article also its says that AMD dual can recognized 2 logical cores

 

[mamisano]

Originally posted by: ahock
yes but from the article also its says that AMD dual can recognized 2 logical cores

NO, it doesn't.

 

[XBoxLPU]

Confirmed

 

[XBoxLPU]

Originally posted by: ahock
Isn't it that hyper threading is a proprietary technology of Intel? Are they allowed to copy this similar to SSE instructions?

AMD owns the patent

SSE3 doesn't mean HT.....

 

[GRIdpOOL]

Don't get worked up. None of us know how this thing will work yet. We are ONLY speculating here. Don't get upset.

 

[StormRider]

It seems like when HT enabled programs are run on an Intel chip, the two threads are run on the same CPU (but being executed at the same time in two different functional units on that same CPU).

If that same program is run on the Dual Core Athlon, then the two threads are run on the two cores at the same time.

But the thing is that the program itself cannot tell how the two threads are being run.

 

[XBoxLPU]

Originally posted by: GRIdpOOL
Don't get worked up. None of us know how this thing will work yet. We are ONLY speculating here. Don't get upset.

We should know more by tomorrow

 

[GRIdpOOL]

DC Opteron
This was hijacked from another post. The dual-core Opteron shows hyper-threading.

 

[XBoxLPU]

Originally posted by: GRIdpOOL
DC Opteron
This was hijacked from another post. The dual-core Opteron shows hyper-threading.

Thats what I just posted
:disgust:

 

[GRIdpOOL]

Too quick for me! Thanks for the post. Lets see what we get tomorrow.

 

[MBrown]

This is exciting.

 

[Aenslead]

Thing is, people... we are speculating a tad bit.

See, HyperThreading was implemented out of necessity on P4 due to its HUGE pipeline and the incredible penalities involved in an empty/idle pipeline; AMD's pipeline is CONSIDERABLY smaller (hence the low latency it has shown since the XP days).

This bit is meant to make HT optimized apps use more of A64's resources, like a better use of the twin 1Mb caches.

Pretty smart from AMD: using existing technology that already has optimizations on important software. now that its fully functional.

And that is all I have to say about that.

 

[Lithan]

If indeed the HT "bit" is enabled to allow the dual core procs to make use of HT enabled software, then the processor would show up as having HT when in fact it didn't actually use HT per se.

 

[bersl2]

If anybody want to now start using a vendor-neutral, marketing-free term for "Hyperthreading," you can say "simultaneous multi-threading" or "SMT."

Just FYI.

 

[91TTZ]

Originally posted by: GRIdpOOL
Hmmm...
It looks like we could be in for more surprises over the next few weeks. I was geared up for a Venice, but now I am anxious to see what is fact and what is fiction about the X2.

I'm thinking that the difference you see is due to the dual core Athlons having 2 cores, with each core having a unique ID and being able to handle its own thread. In other words, neither core is hyperthreaded, but since you now have 2 cores to work with they can now handle hyperthreaded instructions like single core Intel HT chips can.