How to take 50% market share in three years.

[yulgrhet]

This is utter speculation on your part. You are building a house of cards on speculations like this and arguing that the final outcome has some factual value. It really doesn't.

I actually read your post. Once again someone pooh pooh my conclusions while not addressing the particulars any of the points.

I find the 8 core version least likely. Even 4C CCX x2 (8cores) is already kind of overkill for desktop, so jumping to 8C CCX and thus 16 core desktop, just pushes things where they don't need to go

Right, because AMD has no interest in the server market and so a 4 core CCX is fine for the time being.

8C CCX/16 core desktop is probably more expensive to produce than the current die, while you still need parts at desktop prices, so it isn't really the most profitable outcome, and ultimately profit is what they are after.

I covered in exhaustive detail how and why AMD would go with an 8 core CCX.

AMD just doubled Threadripper, why not Ryzen AT 7NM. The idea is to keep Intel back footed and thoroughly uncompetitive.

 

[PeterScott]

Right, because AMD has no interest in the server market and so a 4 core CCX is fine for the time being.

That's an absurd statement.

AFAIK, AMD Epyc already has more cores than anything even on Intels leaked road-map, and AMD will sell you more cores, than the Intel offering at half the price. So more cores and less the half the cost/core.

Anyone who can be swayed by core count and price/core, already has all the reason they need to go with AMD. Simply amping it up because you think they need more overkill is not an argument.

AMD not doing what you think they should, is not a sign they have no interest in a market where the already have the most competetive product.

 

[maddie]

That's an absurd statement.

AFAIK, AMD Epyc already has more cores than anything even on Intels leaked road-map, and AMD will sell you more cores, than the Intel offering at half the price. So more cores and less the half the cost/core.

Anyone who can be swayed by core count and price/core, already has all the reason they need to go with AMD. Simply amping it up because you think they need more overkill is not an argument.

AMD not doing what you think they should, is not a sign they have no interest in a market where the already have the most competetive product.

You are contradicting yourself to advance an argument.

How many times we have heard from you that CPU plans are made years in advance?

Could AMD have predicted 4 years ago that Intel would be stuck on 10nm?
Could AMD upon realizing, a couple years ago at most, that they would now appear to have a major core count advantage, change all plans in motion to "cool it a bit"?

AMD is following a plan laid out many years ago, and it will happen, barring a major unforeseen problem, irrespective of what Intel is doing. At present they will be making predictions for the long term future.

I have stopped responding to most, alas not all, of your posts as I realize the main objective is simply to argue.

 

[NTMBK]

That's an absurd statement.

AFAIK, AMD Epyc already has more cores than anything even on Intels leaked road-map, and AMD will sell you more cores, than the Intel offering at half the price. So more cores and less the half the cost/core.

Anyone who can be swayed by core count and price/core, already has all the reason they need to go with AMD. Simply amping it up because you think they need more overkill is not an argument.

AMD not doing what you think they should, is not a sign they have no interest in a market where the already have the most competetive product.

Cascade Lake AP is apparently a 56 core MCM. AMD need to step up, 32 cores won't cut it! I've seen 64 cores rumoured in a few places.

 

[Timorous]

There are numerous reports from normally reliable sources. It won't be long before someone working on an actual sample leaks detailed info. And it's utterly logical AMD went that route.

The problem with an 8C CCX is that the number of connections each core needs to communicate with every other core grows very quickly. 4C needs 6 connections, 6C needs 15 connections and 8C needs 28 connections. So double the cores needs more than 4x the connections.

The other question is layout, how do you place 8C so that the are equidistant from each other to make core to core communication latency equal for all cores? I think it is doable (not actually tried) but its not an efficient layout where as 2x2 is really space efficient.

Then there is yield, an 8C CCX @ 7nm will be the same size (roughly) as the current 4C CCX at 12nm. Considering that it is reasonable to expect yields of 7nm to be lower than that of 12nm it makes sense to make the CCX smaller to increase the number of working dies per wafer.

Instead of adding more cores to a CCX it makes more sense to just add more CCXs to the module. That way AMD could come out with an initial 3CCX design to have a 48C EPYC and when yields of the 7nm processes improve they can come out with a 4CCX design to have a 64C EPYC.

I just don't see an 8C CCX being used. I may be wrong but I think sticking with the 4C CCX for now and scaling the number of CCXs used in each chip is an easier way to to go.

 

[Vattila]

6C needs 15 connections and 8C needs 28 connections.

Which means that direct connection no longer is feasible, and you will need to move to a slower and more complex interconnection scheme, such as a ring-bus, costing latency and efficiency.

It seems many CPU enthusiasts, with a strange aversion to the slight NUMA introduced by Zen's inter-CCX communication, dearly want this. But the notion that AMD's version of a ring-bus would be as fast and efficient as Intel's implementation is premature, and in my view, unlikely, since Intel has perfected their implementation over a long time. It is much more likely that AMD can bring down inter-core latency by optimising the 4-core CCX — both the latency within a CCX and the average latency across a chip.

Also, what is overlooked, is that a 6-core CCX, or even a 8-core CCX, does not scale much better than a 4-core CCX when it comes to server-grade core counts.

For all those reasons, a 4-core CCX seems very zen to me — and I become very sceptical when I read rumours that claim 6-core or 8-core CCX.

See: Speculation: The CCX in Zen 2

 

[blublub]

The problem with an 8C CCX is that the number of connections each core needs to communicate with every other core grows very quickly. 4C needs 6 connections, 6C needs 15 connections and 8C needs 28 connections. So double the cores needs more than 4x the connections.

The other question is layout, how do you place 8C so that the are equidistant from each other to make core to core communication latency equal for all cores? I think it is doable (not actually tried) but its not an efficient layout where as 2x2 is really space efficient.

Then there is yield, an 8C CCX @ 7nm will be the same size (roughly) as the current 4C CCX at 12nm. Considering that it is reasonable to expect yields of 7nm to be lower than that of 12nm it makes sense to make the CCX smaller to increase the number of working dies per wafer.

Instead of adding more cores to a CCX it makes more sense to just add more CCXs to the module. That way AMD could come out with an initial 3CCX design to have a 48C EPYC and when yields of the 7nm processes improve they can come out with a 4CCX design to have a 64C EPYC.

I just don't see an 8C CCX being used. I may be wrong but I think sticking with the 4C CCX for now and scaling the number of CCXs used in each chip is an easier way to to go.

8c makes only sense if AMD moves the uncore part to a different chip - so the core chip is smaller and yields are better. The author of this thread addressed that, it looks like you missed that part

 

[blublub]

Didn't Intel ditch the Ringbus and changed to Mesh-Interconnects because Ringbus was too slow with over 20-28 cores

 

[scannall]

The problem with an 8C CCX is that the number of connections each core needs to communicate with every other core grows very quickly. 4C needs 6 connections, 6C needs 15 connections and 8C needs 28 connections. So double the cores needs more than 4x the connections.

The other question is layout, how do you place 8C so that the are equidistant from each other to make core to core communication latency equal for all cores? I think it is doable (not actually tried) but its not an efficient layout where as 2x2 is really space efficient.

Then there is yield, an 8C CCX @ 7nm will be the same size (roughly) as the current 4C CCX at 12nm. Considering that it is reasonable to expect yields of 7nm to be lower than that of 12nm it makes sense to make the CCX smaller to increase the number of working dies per wafer.

Instead of adding more cores to a CCX it makes more sense to just add more CCXs to the module. That way AMD could come out with an initial 3CCX design to have a 48C EPYC and when yields of the 7nm processes improve they can come out with a 4CCX design to have a 64C EPYC.

I just don't see an 8C CCX being used. I may be wrong but I think sticking with the 4C CCX for now and scaling the number of CCXs used in each chip is an easier way to to go.

The package size is quite large. And at 7nm, the dies would be quite small. My guess anyway, is staying at 4C CCX, and just adding more dies since there would be enough room for it.

 

[yulgrhet]

8c makes only sense if AMD moves the uncore part to a different chip - so the core chip is smaller and yields are better. The author of this thread addressed that, it looks like you missed that part

Yes! ... Thank you.

 

[maddie]

8c makes only sense if AMD moves the uncore part to a different chip - so the core chip is smaller and yields are better. The author of this thread addressed that, it looks like you missed that part

The problem I see with this, is the single die desktop part.

Unless AMD is going to abandon the single design for both server & desktop, then they need a complete unit on a single die. Zen2 & Zen3 designs were completed when AMD was just managing to survive financially. I can't see any way for them to have abandoned the Zen1 design philosophy, even if they wanted to do so.

I can see more chiplets [4+] for the server part, but each chiplet must be able to stand alone as a complete CPU.

 

[yulgrhet]

Cascade Lake AP is apparently a 56 core MCM. AMD need to step up, 32 cores won't cut it! I've seen 64 cores rumoured in a few places.

Charlie's

"AMD’s Rome is going to be a monster CPU
Not the monster you expected, much more monstrous

If AMD stuck with it’s 2016 roadmaps, it would be in for a big fight with Intel next year. The roadmaps SemiAccurate and Fudzilla reported back then were not followed and the server market is no longer a fight ... Lets just say the roadmaps are vastly different from those 48-core behemoths envisioned back then. What is AMD planning? A 7nm monster called Rome ..."

article really intrigues me. As does AMD's roadmap 'Improves on "Zen" in multiple dimensions' description of Zen 2.

The 'multiple dimensions' descriptive wasn't on earlier roadmaps. A Lisa Su tease.

A Zen 4 uncore+chiplets architecture is a logical progression on the original roadmap to keep expanding the core count and making better use of future node's wafers.

Looks to me Lisa Su got early confirmation of the true state of Intel's 10nm and put together a team to explore what could be done to take advantage of that opportunity. Changing EPYC 2 to an Uncore architecture had to be top of the list as a team would already be working on it and it enables doubling the number of dies on a 7nm wafer to provide the additional EPYC 2 CPUs needed to take full advantage of that opportunity.

An uncore opens up possibilities on the CCX size and numbers of core chiplets that could fit and work with the uncore chip.

I envision the arrangement as an uncore chip with chiplets branching out horizontally on both sides, With an uncore chip all the inter-core fabric connections would no longer be needed, only a connection of each core to the uncore chip, so all that substrate complexity goes away freeing up layers that can be used to make an uncore arrangement work with existing sockets.

The uncore chip would be large and complex, but on an older mature node, a relative walk in the park. AMD has mentioned on numerous occasions now much more complex architecting and engineering for the 7nm node has been than anything AMD has done before. Putting half the chip on an uncore makes that much easier.

The first iteration of an uncore would balance out the number of attached core chiplets that can be added with the CCX core increase.

The original 48 core plan would have been a 6 core CCX and with a lot of that architecting work already being done staying with that makes sense ... ... I'm now thinking a six core CCX instead of an 8 core CCX. Smaller die and more time to work on adding more features to the architecture. Also aligns with the 12 core Ryzen 2 rumors.

So 12 core chiplets. How expandable is the uncore? There are rumors of a 256 meg L3 cache on the uncore, that is monstrous. Three per side for 72 cores? Four per side for 96 cores? How far do they want to bury Intel? How far can they bury Intel? As deep as possible I would think. Again, Charlie's 'much more monstrous' thing. Sounds like more than 64 cores. A 72 core EPYC 2 and 96 core EPYC 3?

A 72 core EPYC 2 would shake the industry to it's core.

AMD would be patenting all this so Intel would be SOL copying AMD.

Zen 3 - in addition to the improvements 7nm+ brings, maybe 96 cores and this might be when that SMT >2 rumor comes into play, adding AI and graphics elements to the uncore and chiplet cores to substantially increase SMT efficiency. A 96 core 382 thread EPYC 3 CPU? That would be up against, at best, a dual 14nm 28 core cpus on a substrate space heater?

A 72/96 core EPYC 2 would storm the tech and financial press and be widely picked up by the mainstream press, all with headlines and comparisons dragging Intel's name and reputation through the mud.

Intel's server market would be in an arterial bleed-out. Along with all it's other x86 markets.

This is a realistic scenario and all credible rumors to date and simple logic lead to just that scenario.

Intel is living in very interesting times indeed.

 

[Gideon]

The problem I see with this, is the single die desktop part.

Unless AMD is going to abandon the single design for both server & desktop, then they need a complete unit on a single die. Zen2 & Zen3 designs were completed when AMD was just managing to survive financially. I can't see any way for them to have abandoned the Zen1 design philosophy, even if they wanted to do so.

I can see more chiplets [4+] for the server part, but each chiplet must be able to stand alone as a complete CPU.

Overall I agree, though there are some signs that they might abandon the same die strategy for desktop and server:

1. We know that Rome is built @ TSMC and there are rumours that Ryzen 3xxx being built @ Glo-Fo. It would make some sense, as the TSMC process is earlier to market, yet apparently doesn't allow very high clock-speeds (at least compared to the GF 7nm IBM-derived process).Therefore it wouldn't be that suitable to desktop 4+ GHz designs anyway. It probably has better power characteristics @ lower clocks though.

2. If Desktop and Server chips are different dies, then there are better optimisation avenues for both. E.g. EPYC Multi-Chip latency could be improved considerably if an interposer were used instead of plain MCM. You can't do that and preserve compatibility unless you want every desktop part to have an interposer as well.

3. Adding a passive interposer to EPYC would make sense as a middle step between the current chips and chiplets on an active interposer - which AMD has to do eventually anyway

Personally I'm not convinced AMD can afford multiple dies already (especially as 7nm is a whole lot more expensive than 14nm), but I also wouldn't rule it out entirely.

I'm even less convinced that they were willing to take the risks of adding an interposer to every EPYC 2 chip (as any problems with that would postpone the entire launch). But i still think we will see them at some point. whether it's the 64 Core Zen2 or Zen3 ... who knows

 

[maddie]

Overall I agree, though there are some signs that they might abandon the same die strategy for desktop and server:

1. We know that Rome is built @ TSMC and there are rumours that Ryzen 3xxx being built @ Glo-Fo. It would make some sense, as the TSMC process is earlier to market, yet apparently doesn't allow very high clock-speeds (at least compared to the GF 7nm IBM-derived process).Therefore it wouldn't be that suitable to desktop 4+ GHz designs anyway. It probably has better power characteristics @ lower clocks though.

2. If Desktop and Server chips are different dies, then there are better optimisation avenues for both. E.g. EPYC Multi-Chip latency could be improved considerably if an interposer were used instead of plain MCM. You can't do that and preserve compatibility unless you want every desktop part to have an interposer as well.

3. Adding a passive interposer to EPYC would make sense as a middle step between the current chips and chiplets on an active interposer - which AMD has to do eventually anyway

Personally I'm not convinced AMD can afford multiple dies already (especially as 7nm is a whole lot more expensive than 14nm), but I also wouldn't rule it out entirely.

I'm even less convinced that they were willing to take the risks of adding an interposer to every EPYC 2 chip (as any problems with that would postpone the entire launch). But i still think we will see them at some point. whether it's the 64 Core Zen2 or Zen3 ... who knows

(1) Agree with possibility.

(2) Agree with 1st part, disagree with last part.
"EPYC Multi-Chip latency could be improved considerably if an interposer were used instead of plain MCM. You can't do that and preserve compatibility unless you want every desktop part to have an interposer as well."
Using a CPU chiplet on an interposer does not exclude using it on a traditional package substrate. We're not talking about HBM memory connection density here, which is simply impossible to do otherwise.

(3) Agree

 

[PeterScott]

The problem with an 8C CCX is that the number of connections each core needs to communicate with every other core grows very quickly. 4C needs 6 connections, 6C needs 15 connections and 8C needs 28 connections. So double the cores needs more than 4x the connections.

The other question is layout, how do you place 8C so that the are equidistant from each other to make core to core communication latency equal for all cores? I think it is doable (not actually tried) but its not an efficient layout where as 2x2 is really space efficient.

Then there is yield, an 8C CCX @ 7nm will be the same size (roughly) as the current 4C CCX at 12nm. Considering that it is reasonable to expect yields of 7nm to be lower than that of 12nm it makes sense to make the CCX smaller to increase the number of working dies per wafer.

Instead of adding more cores to a CCX it makes more sense to just add more CCXs to the module. That way AMD could come out with an initial 3CCX design to have a 48C EPYC and when yields of the 7nm processes improve they can come out with a 4CCX design to have a 64C EPYC.

I just don't see an 8C CCX being used. I may be wrong but I think sticking with the 4C CCX for now and scaling the number of CCXs used in each chip is an easier way to to go.

I agree. This is exactly what I was getting at when I mentioned how elegant the 4C CCX is, and how it gets a lot messier with 6C-8C CCX.

Doing a 12 core die with 3 CCX modules, is MUCH simpler iteration, and also agree that would also be a more sensible step on a new process than going straight for 16 core dies.

It's not hard to imaging that 4C CCX, was seen as scaling up to 4 of them. You have the simple internal 4 way connection, and you can have that same simple 4 way connections between the CCXs.

So you can see the simple scaling between 1CCX to 4 CCX, giving 4-16 cores per die. Unless there is a dire need, simple almost always wins over complex. In this case simple is more CCX modules, complex is more cores in the CCX.

Once you reach 16 Cores, then you may have a redo on topology ( Mesh?), because you are facing complexity either way.

 

[Genx87]

Well, there are some really good AMD servers out there:

From https://www.servethehome.com/dell-emc-poweredge-r7415-review/

"The Dell EMC PowerEdge R7415 is an insanely good server. In fact, it may be the best single socket server on the planet. The server features a single socket AMD EPYC platform with an enormous capacity for high-speed networking, NVMe storage, memory capacity, cores counts, and just about every other aspect that makes a server good. In our Dell EMC PowerEdge R7415 review we are going to go in-depth to show you why this is a disruptive server regarding price, performance, and capabilities. "

That is great. When I am looking into single socket servers(never) I will look at this one. But the issue is even if AMD had a clear advantage. Do they have the manufacturing capacity to make it to 50%?

 

[scannall]

That is great. When I am looking into single socket servers(never) I will look at this one. But the issue is even if AMD had a clear advantage. Do they have the manufacturing capacity to make it to 50%?

Possibly. TSMC has a lot of capacity. But I think that %50 so fast is a bit out there.

 

[bauerbrazil2014]

More rumors about Intel on Semiaccurate.

Intel has no chance in servers and they know it
https://semiaccurate.com/2018/08/07/intel-has-no-chance-in-servers-and-they-know-it/

 

[NTMBK]

I agree. This is exactly what I was getting at when I mentioned how elegant the 4C CCX is, and how it gets a lot messier with 6C-8C CCX.

Doing a 12 core die with 3 CCX modules, is MUCH simpler iteration, and also agree that would also be a more sensible step on a new process than going straight for 16 core dies.

It's not hard to imaging that 4C CCX, was seen as scaling up to 4 of them. You have the simple internal 4 way connection, and you can have that same simple 4 way connections between the CCXs.

So you can see the simple scaling between 1CCX to 4 CCX, giving 4-16 cores per die. Unless there is a dire need, simple almost always wins over complex. In this case simple is more CCX modules, complex is more cores in the CCX.

Once you reach 16 Cores, then you may have a redo on topology ( Mesh?), because you are facing complexity either way.

Charlie's

"AMD’s Rome is going to be a monster CPU
Not the monster you expected, much more monstrous

If AMD stuck with it’s 2016 roadmaps, it would be in for a big fight with Intel next year. The roadmaps SemiAccurate and Fudzilla reported back then were not followed and the server market is no longer a fight ... Lets just say the roadmaps are vastly different from those 48-core behemoths envisioned back then. What is AMD planning? A 7nm monster called Rome ..."

article really intrigues me. As does AMD's roadmap 'Improves on "Zen" in multiple dimensions' description of Zen 2.

The 'multiple dimensions' descriptive wasn't on earlier roadmaps. A Lisa Su tease.

A Zen 4 uncore+chiplets architecture is a logical progression on the original roadmap to keep expanding the core count and making better use of future node's wafers.

Looks to me Lisa Su got early confirmation of the true state of Intel's 10nm and put together a team to explore what could be done to take advantage of that opportunity. Changing EPYC 2 to an Uncore architecture had to be top of the list as a team would already be working on it and it enables doubling the number of dies on a 7nm wafer to provide the additional EPYC 2 CPUs needed to take full advantage of that opportunity.

An uncore opens up possibilities on the CCX size and numbers of core chiplets that could fit and work with the uncore chip.

I envision the arrangement as an uncore chip with chiplets branching out horizontally on both sides, With an uncore chip all the inter-core fabric connections would no longer be needed, only a connection of each core to the uncore chip, so all that substrate complexity goes away freeing up layers that can be used to make an uncore arrangement work with existing sockets.

The uncore chip would be large and complex, but on an older mature node, a relative walk in the park. AMD has mentioned on numerous occasions now much more complex architecting and engineering for the 7nm node has been than anything AMD has done before. Putting half the chip on an uncore makes that much easier.

The first iteration of an uncore would balance out the number of attached core chiplets that can be added with the CCX core increase.

The original 48 core plan would have been a 6 core CCX and with a lot of that architecting work already being done staying with that makes sense ... ... I'm now thinking a six core CCX instead of an 8 core CCX. Smaller die and more time to work on adding more features to the architecture. Also aligns with the 12 core Ryzen 2 rumors.

So 12 core chiplets. How expandable is the uncore? There are rumors of a 256 meg L3 cache on the uncore, that is monstrous. Three per side for 72 cores? Four per side for 96 cores? How far do they want to bury Intel? How far can they bury Intel? As deep as possible I would think. Again, Charlie's 'much more monstrous' thing. Sounds like more than 64 cores. A 72 core EPYC 2 and 96 core EPYC 3?

A 72 core EPYC 2 would shake the industry to it's core.

AMD would be patenting all this so Intel would be SOL copying AMD.

Zen 3 - in addition to the improvements 7nm+ brings, maybe 96 cores and this might be when that SMT >2 rumor comes into play, adding AI and graphics elements to the uncore and chiplet cores to substantially increase SMT efficiency. A 96 core 382 thread EPYC 3 CPU? That would be up against, at best, a dual 14nm 28 core cpus on a substrate space heater?

A 72/96 core EPYC 2 would storm the tech and financial press and be widely picked up by the mainstream press, all with headlines and comparisons dragging Intel's name and reputation through the mud.

Intel's server market would be in an arterial bleed-out. Along with all it's other x86 markets.

This is a realistic scenario and all credible rumors to date and simple logic lead to just that scenario.

Intel is living in very interesting times indeed.

The fundamental problem with that uncore vision is that the central chip with memory controllers will become extremely complex and hot. It will have to handle all of the cache coherency traffic between all of those dies, as well as handling all requests to main memory. You've replaced a distributed network with a single bottleneck!

 

[moonbogg]

I'm sure I predicted all this. Search my posting history and cherry pick as needed to verify my prophetic abilities are legit.

 

[maddie]

I'm not advocating any position here, but simply trying to understand.

Every single, admittedly "back of the envelope calculation" I do has AMD being able to produce enough CPUs for 50% marketshare. In opposition to the commonly held belief by many, I don't see production capacity as a limit to growth. We will have to look elsewhere to know why they can't achieve 50%.

The method I used was simply using Intel's server revenue and assuming a rough sales price of $80 / core. Extremely rough calcs but they can provide some guidelines and trying to make it very conservative, I assumed all revenue in the group went to CPUs and the price was very low per core. Both decisions had the effect of inflating the core production number, making it worse for AMD.

Year 2016 Intel
Server = $ 17.226B [29% of $59.4B]
Cores = 215 Million [$80/core]

For AMD we need 107 Million cores [50%]
Equals 13.5 million 8C dies.

On 14nm, this is roughly 5000 wafers/month @ 216 210mm^2 die/wafer [0.1 defect rate /sq. cm] [300mm diameter]

On 7nm, I get roughly 2500 wafers/month @ 446 100mm^2 die /wafer [0.3 defect rate /sq. cm] [300mm diameter]

What am I doing wrong, as this goes against everything I read from most sites and posters?

 

[Trumpstyle]

Do we know yet how many cores the CCX will have?

What I gathered from the most reliable rumors on the internet, the server ccx will have 8 cores and the desktop will have 6 cores.

I'm not a hardware engineer but the server die will have 4 chip with each having 2x ccx giving it a total 64 cores and another chip that has cache and stuff, giving this die a total of 5 chips (4 chips with cores, 1 chip with cache).

Let's see what happens.

 

[blublub]

The problem I see with this, is the single die desktop part.

Unless AMD is going to abandon the single design for both server & desktop, then they need a complete unit on a single die. Zen2 & Zen3 designs were completed when AMD was just managing to survive financially. I can't see any way for them to have abandoned the Zen1 design philosophy, even if they wanted to do so.

I can see more chiplets [4+] for the server part, but each chiplet must be able to stand alone as a complete CPU.

If AMDs plan was along to go "uncore" via chipsets you might be wrong. The Zen and Infinity fabric design is really flexible even with Zen1 - look at TR2 32c with only 4 mem channels, 2 dies are just "core cpu" and are connected to the other 2 for memory.

After the SA article from Charlie how REDACTED Intel is I am more willing to believe in the 64c version of Rome - however I am still extremly sceptical about the uncore version an it still seems far fetched that AMD can pull that if from Gen1 to Gen2

Profanity is not allowed in the Tech sub-forums.

Iron Woode
Super Moderator

 

[blublub]

I can see more chiplets [4+] for the server part, but each chiplet must be able to stand alone as a complete CPU.

Since AMD has more money now and uses TSMC and GloFo, which means they need to adapt the masks and design to a different process anyways, I thin a selerat desktop version is very likely - server tsmc, desktop glofo

 

[Shivansps]

3CCX and a Vega block i wonder if they dan do 3-channel memory.

I agree. This is exactly what I was getting at when I mentioned how elegant the 4C CCX is, and how it gets a lot messier with 6C-8C CCX.

Doing a 12 core die with 3 CCX modules, is MUCH simpler iteration, and also agree that would also be a more sensible step on a new process than going straight for 16 core dies.

It's not hard to imaging that 4C CCX, was seen as scaling up to 4 of them. You have the simple internal 4 way connection, and you can have that same simple 4 way connections between the CCXs.

So you can see the simple scaling between 1CCX to 4 CCX, giving 4-16 cores per die. Unless there is a dire need, simple almost always wins over complex. In this case simple is more CCX modules, complex is more cores in the CCX.

Once you reach 16 Cores, then you may have a redo on topology ( Mesh?), because you are facing complexity either way.

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