Can you expand upon this, or break it down in dummy language? Is it power 'density' or just voltage limitations? How are these guys getting 5Ghz+ out of some CPUs besides tremendous cooling?
VLSI means very large scale integration, and in dummy language it basically describes the class of manufacturing our CPUs belong to: close to a billion tiny adjacent transistors. technically even more than a billion since we're talking 32nm.
you will never have all of these transistors operating at insane frequencies simultaneously, but the concept of turbo mode is going to become increasingly finer-grained to the point where you will see all the resources you need at high frequencies, but not the entire chip. the voltage required to have over a billion ~32nm transistors running at 4.5+ GHz is probably perfectly safe for most specimens and when the time comes the overclocking community will manage it, but the resistive heating due to the increased current would still produce more heat than intel is willing to deal with because they have to come up with a free heatsink to give you and it's going to be a piece of shit. as a conductor warms, the additional heat-per-amp dissipated increases quadratically* with temp, which is why 5.5 GHz is impossible to do at 70 degrees but perfectly fine at 10 degrees. is intel going to buy you a cooling system that does that? heh they should for what the extreme editions cost. but whatever, it makes high frequencies seem more alluring to us.
sandy bridge turbo modes will definitely be breaking into the 4 ghz region but probably only one physical core (the 1155 variant only goes up to 3.8 on one core; expect the larger brothers to surpass that) out of a 80-130 watt chip, which is totally safe. i'd even say it's on the pussy side of safe. just like the D0 i7's, there will be plenty of users breaking into 4+ GHz on the stock cooler, we'll just have to wait and see. in regard to future architectures, as turbo evolves into intra-core clock adjustment capability, we will hopefully start to see higher frequency ALU/FPU, cache, and MCH capability with perhaps lower-frequency decode and thread scheduling in the future. certainly not next year, but in the future you can expect more and more components to be compartmentalized into clock domains so that the dissipative power budget of the processor can be economized. hopefully AMD is realizing this opportunity with Bulldozer given the intra-core modularity and reputation for high TDP. AMD and intel will certainly use discrete domains on their IGPs and PCIe controllers if they are to be brought into the uncore.
*keeping it simple for the sake of discussion. the heat energy crosses numerous molecular boundaries and forming a remotely accurate mathematical generalization becomes tiresome. if you really want to know you can just
read about each transfer mechanism individually.
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