How are modern clock speeds possible?

[beer]

So I'm taking a second-semester digital systems design class. We're using Xilinix FGPAs and associated tools for synthesis, modelsim for simulation, etc, your typical third year level class. So I know FPGAs aren't exactly high-tech, but after I'm done synthesizing and translating, even with simple circuits (such as counters and registers), the maximum clock speed of any of my circuits is around 150 MHz. Anything above that, gate delays cause the flipflops to lose stability and make stuff break.

So if a clock is running at 3 GHz, the maximum delay across a single flipflop would be on the order of 1/3 of a nanosecond - assuming NO combinational or supporting sequential logic. How is this possible? All the flip-flops I have ever seen have setup and hold times an order of magnitiude higher. Are the devices that intel uses just so much more advanced and have process constants that low? Or it something else?

It just blows my mind that devices can be stable in the GHz range. And, on top of that, generate so little capacitence too

 

[SuperTool]

Originally posted by: beer
So I'm taking a second-semester digital systems design class. We're using Xilinix FGPAs and associated tools for synthesis, modelsim for simulation, etc, your typical third year level class. So I know FPGAs aren't exactly high-tech, but after I'm done synthesizing and translating, even with simple circuits (such as counters and registers), the maximum clock speed of any of my circuits is around 150 MHz. Anything above that, gate delays cause the flipflops to lose stability and make stuff break.

So if a clock is running at 3 GHz, the maximum delay across a single flipflop would be on the order of 1/3 of a nanosecond - assuming NO combinational or supporting sequential logic. How is this possible? All the flip-flops I have ever seen have setup and hold times an order of magnitiude higher. Are the devices that intel uses just so much more advanced and have process constants that low? Or it something else?

It just blows my mind that devices can be stable in the GHz range. And, on top of that, generate so little capacitence too

If I designed a flop and delay was 333ps, I would put a gun in my mouth and pull the trigger
Good modern flop designs, like pulse latches and semidynamic or dynamic flip flops, in latest fab process have delays one order of magnitude lower. 333ps is delay for flop and logic to next flop.
Also, you may not be aware of this, but Intel's integer unit runs at 2x the frequency or 6 ghz, which is one of the reasons they are having problems scaling it to 4ghz, because that would mean integer unit has to run at 8ghz.
http://www.stanford.edu/class/...ctures/lect_07_2up.pdf
has a good description of many modern clocked storage elements.
As you can see, the fast ones have delays of 2.5 fanout 4 inverter delays, which in a modern process is less than 50ps by a good margin.

 

[TuxDave]

Originally posted by: beer
So I'm taking a second-semester digital systems design class. We're using Xilinix FGPAs and associated tools for synthesis, modelsim for simulation, etc, your typical third year level class. So I know FPGAs aren't exactly high-tech, but after I'm done synthesizing and translating, even with simple circuits (such as counters and registers), the maximum clock speed of any of my circuits is around 150 MHz. Anything above that, gate delays cause the flipflops to lose stability and make stuff break.

So if a clock is running at 3 GHz, the maximum delay across a single flipflop would be on the order of 1/3 of a nanosecond - assuming NO combinational or supporting sequential logic. How is this possible? All the flip-flops I have ever seen have setup and hold times an order of magnitiude higher. Are the devices that intel uses just so much more advanced and have process constants that low? Or it something else?

It just blows my mind that devices can be stable in the GHz range. And, on top of that, generate so little capacitence too

There are widely used papers on senseamp flip-flops in 0.18um technology that could achieve delays of 230ps, setup times of -25ps and hold times of 100ps. You have to realize that FPGAs cannot achieve anywhere close to the optimal power or delay numbers that an custom design can. What FPGAs CAN do is make create chips at a faster turnaround time. I'm working with 90nm technology at my university which gives me FO4 inverter delays at around 20-30ps. Quite speedy stuff. I'm a little rusty on architecture but if you want a speedy datapath, I thought that you would divide up combinational logic with latches and not flip-flops so you can use time-borrowing/etc...

 

[beer]

Originally posted by: TuxDave
There are widely used papers on senseamp flip-flops in 0.18um technology that could achieve delays of 230ps, setup times of -25ps and hold times of 100ps. You have to realize that FPGAs cannot achieve anywhere close to the optimal power or delay numbers that an custom design can. What FPGAs CAN do is make create chips at a faster turnaround time. I'm working with 90nm technology at my university which gives me FO4 inverter delays at around 20-30ps. Quite speedy stuff. I'm a little rusty on architecture but if you want a speedy datapath, I thought that you would divide up combinational logic with latches and not flip-flops so you can use time-borrowing/etc...

Well, at the level I'm at the mindset is latches = universally bad since if your synthesis report contains latches, it means your circuit has severe timing issues and basically that your design sucks. Since I'm not familiar with timeborrowing or anything like that, I'll just smile and nod

 

[TuxDave]

Originally posted by: beer

Originally posted by: TuxDave
There are widely used papers on senseamp flip-flops in 0.18um technology that could achieve delays of 230ps, setup times of -25ps and hold times of 100ps. You have to realize that FPGAs cannot achieve anywhere close to the optimal power or delay numbers that an custom design can. What FPGAs CAN do is make create chips at a faster turnaround time. I'm working with 90nm technology at my university which gives me FO4 inverter delays at around 20-30ps. Quite speedy stuff. I'm a little rusty on architecture but if you want a speedy datapath, I thought that you would divide up combinational logic with latches and not flip-flops so you can use time-borrowing/etc...

Well, at the level I'm at the mindset is latches = universally bad since if your synthesis report contains latches, it means your circuit has severe timing issues and basically that your design sucks. Since I'm not familiar with timeborrowing or anything like that, I'll just smile and nod

Just wait until you get into a real circuit design class instead of the FPGA/CAD class you're taking. Assuming you have the best design and some pipelined topology. If you use latches, you may be able to clock your circuit faster than if you had flip-flops.

 

[beer]

Originally posted by: TuxDave

Just wait until you get into a real circuit design class instead of the FPGA/CAD class you're taking. Assuming you have the best design and some pipelined topology. If you use latches, you may be able to clock your circuit faster than if you had flip-flops.

So are you essentially saying that most of the stuff clocked beyond FGPA speeds I'm dealing with (~150 MHz) (things like some of the DSP stuff I'm handling in my other classes, etc) is run by stuff that isnt even edge-triggered?

 

[TuxDave]

Originally posted by: beer

Originally posted by: TuxDave

Just wait until you get into a real circuit design class instead of the FPGA/CAD class you're taking. Assuming you have the best design and some pipelined topology. If you use latches, you may be able to clock your circuit faster than if you had flip-flops.

So are you essentially saying that most of the stuff clocked beyond FGPA speeds I'm dealing with (~150 MHz) (things like some of the DSP stuff I'm handling in my other classes, etc) is run by stuff that isnt even edge-triggered?

I don't recall the exact situation where you need edge triggered flip-flops, but anyways, here's how you can use latches in place of flip-flops.

C.L. = Combinational Logic
H.P. = High Pass Latch (transparent on high)
L.P. = Low Pass Latch (transparent on low)

CL -> HP -> CL -> LP -> CL -> HP -> CL....

Do you see how you can pipeline with latches?

 

[SuperTool]

I wouldn't say most isn't edge triggered. A lot of companies use edge triggered flops, because latch based timing gets kind of tricky if you have loops, and also, you have two latches per cycle that add to overhead, and that you have to check mintime races for. Latches mainly help you by absorbing skew because they allow time borrowing across the latch. Many companies use pulse latches, which act as edge triggered flops with a little bit of transparency for skew tolerance dictated by the pulse width. Some use a mixture of latches and flops with most logic using flops, and latches only used where necessary to meet timing target. Latches are good for dynamic logic, because every dynamic gate can act as a latch.

 

[dmw16]

I know it isnt too technical. But all this stuff if F(vcking)M(agic) to me. I am an aerospace engineering major, but I didnt do too well in my obligatory electronics class. It's all just too small.

 

[beer]

Originally posted by: dmw16
I know it isnt too technical. But all this stuff if F(vcking)M(agic) to me. I am an aerospace engineering major, but I didnt do too well in my obligatory electronics class. It's all just too small.

I mean I'm a 3rd yr EE and already this stuff, that I was talking about, is into the elective category - not even required of the majority of EEs. What Tuxdave and Supertool are talking about is pretty much at the MS level, I think; beyond what even a BSEE needs to understand.

 

[TOTA42]

I'm a 4th year EE at UT and I don't even remember hearing any of this stuff, what class are you taking that you deal with this? The only time I messed with FPGAs is EE321k.

 

[beer]

Originally posted by: TOTA42
I'm a 4th year EE at UT and I don't even remember hearing any of this stuff, what class are you taking that you deal with this? The only time I messed with FPGAs is EE321k.

EE360M - using roth's VHDL book
Prof Lizy John is teaching it - its an elective and only is pre-approved for embedded systems, but'it's offered every semester. In fact the lab is right next to the 317 LRC

EDIT: also it looks like you're on the 00-02 catalog. We did a bit of FPGA work in 316 using the new books, he wrote in 3 chapters of VHDL on top of everything else (yay for us). Of course the stuff in 316 was pretty basic compared to this, still, it's in the core cirriculum now.

I don't have to take 321k (nor do I intend to)

 

[TuxDave]

Originally posted by: beer

Originally posted by: dmw16
I know it isnt too technical. But all this stuff if F(vcking)M(agic) to me. I am an aerospace engineering major, but I didnt do too well in my obligatory electronics class. It's all just too small.

I mean I'm a 3rd yr EE and already this stuff, that I was talking about, is into the elective category - not even required of the majority of EEs. What Tuxdave and Supertool are talking about is pretty much at the MS level, I think; beyond what even a BSEE needs to understand.

Well... it all depends on your focus. If you go hardcore into circuits meaning you take all the ugrad analog/digital circuits classes, you will learn what I'm talking about. Seeing how you're doing VHDL and working with FPGAs I'm guessing you're leaning towards the Computer Engineering area so you'll be more familiar with CAD tools and less with detailed circuit design.

 

[RaynorWolfcastle]

beer, basic CAD is an Elective for EEs? Wow, it's required here: both a VHDL lab and an intro to digital system design. The stuff we learned is mostly the kind of thing you're talking about, though we do everything with an Altera board rather than a Xilinx.
Also, the cool thing here is that all EEs/CEs have to take an analog electronics class in which we have design a 3 stage amplfier design that we actually get fabbed and use in the lab. It's pretty sweet, though we have to use a freeware tool for layout because Cadence is too expensive to use on the scale of 40 groups/semester. Nonetheless, it's pretty cool to design your own chip as an undergrad, I've been told that we're one of the only schools that does something of the sort.

edit: Sorry for being OT of the original question, I think that part was already answered though.

 

[TuxDave]

Originally posted by: RaynorWolfcastle
beer, basic CAD is an Elective for EEs? Wow, it's required here: both a VHDL lab and an intro to digital system design. The stuff we learned is mostly the kind of thing you're talking about, though we do everything with an Altera board rather than a Xilinx.
Also, the cool thing here is that all EEs/CEs have to take an analog electronics class in which we have design a 3 stage amplfier design that we actually get fabbed and use in the lab. It's pretty sweet, though we have to use a freeware tool for layout because Cadence is too expensive to use on the scale of 40 groups/semester. Nonetheless, it's pretty cool to design your own chip as an undergrad, I've been told that we're one of the only schools that does something of the sort.

edit: Sorry for being OT of the original question, I think that part was already answered though.

Dude.. they let you fab an amplifier? The hell, all I got to fab was a vertical diode... and EVEN THAT DIDN'T WORK! (mainly because we had a power outage in the baking stage of the implant)

 

[RaynorWolfcastle]

Originally posted by: TuxDave

Originally posted by: RaynorWolfcastle
beer, basic CAD is an Elective for EEs? Wow, it's required here: both a VHDL lab and an intro to digital system design. The stuff we learned is mostly the kind of thing you're talking about, though we do everything with an Altera board rather than a Xilinx.
Also, the cool thing here is that all EEs/CEs have to take an analog electronics class in which we have design a 3 stage amplfier design that we actually get fabbed and use in the lab. It's pretty sweet, though we have to use a freeware tool for layout because Cadence is too expensive to use on the scale of 40 groups/semester. Nonetheless, it's pretty cool to design your own chip as an undergrad, I've been told that we're one of the only schools that does something of the sort.

edit: Sorry for being OT of the original question, I think that part was already answered though.

Dude.. they let you fab an amplifier? The hell, all I got to fab was a vertical diode... and EVEN THAT DIDN'T WORK! (mainly because we had a power outage in the baking stage of the implant)

Yeah getting to fab our own amplifier is pretty sweet, but in reality it's not a fully custom design. We only get to design the top-most metallic layer which is the interconnections, all the electronics are already set. Also, it's a BJT-only design and it's 1 um and we simulate it to death with SPICE to make sure it'll work. Still, I like the lab, and we get to keep the chip once we're done with the class .