Hi all. I will now summarise for those searching the archives.
Thanks to Peter for his help.
host-pci bridge
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* Found on the north bridge [is the north bridge]
* serves the purpose to bridge the CPU to one or more PCI busses
* The root of the PCI system starts at the 'host-pci' bridge
* talks to at least one CPU, hence the word 'host'
* you can extend the host-pci bridge with a pci-pci bridge
* contains a virtual pci-pci bridge that represents AGP
* devices connecting to the north and south bridges show up as one pci bus (bus 0).
pci-pci bridge
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* you can only have a certain number of electrical loads on one bus
and you can make the traces only a limited length. If you want more
devices and/or longer traces you will need a bridge chip.
* Any given pci slot lets you only connect just ONE device. If you
want to create a 'multifunction card' [e.g. DEC21151 chip found on
various four port NICs] you need to put a pci-pci bridge into that
one device position which will create a new separate "on-card" pci
bus which multiple devices can then connect to.
* if we want to have different technology busses in the same system we
can bridge the different 'isolated' busses together with a pci-pci
bridge e.g. pci-x slots as well as traditional 33MHz pci slots i.e. we
bridge the slower slots to the faster slots via a pci-pci bridge.
transparent pci bridge
--------------------------
After the system's BIOS is done setting up the bridge architecture,
device enumeration and usage are implemented without ever touching any
programming feature of the bridge chips.
Once the bridges [pci-pci,host-pci,pci-isa] are set up, configuration
and actual traffic is now able to travel through these bridges
automagically.
Device drivers do not need to have any knowledge about how and when to
get to "their" chip. They can actually ignore the fact of whether or
not their device is on a bridged bus or a native bus.
pci-isa bridge
----------------
From somewhere close to the root of the pci bus you bridge over to the
remains of the ISA bus, where still much of the x86 compatability
hardware is being implemented. Basically any cycle not actively taken
(positively decoded) by a pci device or bridge ends up being forwarded
to the ISA bus. There the cycle is either served by a legacy device or
times out and yields no data.