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Everything should be deterministic >>
But computers aren't deterministic (though for simple performance analysis simulations, treating them as so makes it easier

), even if they were completely solid state. There's just too many variables and events that can take place: cache misses, TLB misses, page faults, IO interupts, exceptions, CPU scheduling, DRAM refreshes, OS system calls, dynamic memory allocation, garbage collection....the list goes on and on. Each of these events can occur at different frequencies, and many have their own variables (a page fault could be dealt with any number of page replacement algorithms, the new page may replace a clean or dirty frame, the replaced page may be of the same or different process of the new page).
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The CPU sends a signal and the memory resoponds exactly 4 clocks later, not 3.85, not 4.21. >>
There's no guarantee that a memory access always takes the same amount of time....a memory access could hit any one of the caches, the main memory, or a paged frame. There are also TLB hits/misses involved for virtual address translations. Even if a memory access does hit the main memory, it doesn't necessarily take the same amount of time....there could be a column/page hit (not to be confused with virtual memory/paging), a page miss, or a precharge event...for most high-performance DRAM, this takes 2, 4, or 6 cycles, respectively. Plus every few milliseconds the DRAM cells have to be refreshed, which takes time. There's also bus arbitration to consider...there may be multiple outstanding memory accesses which may have to compete for the FSB, along with I/O. And if the memory bus is asynchronous with the FSB, there may be an extra cycle while the memory controller waits for the next rising FSB clock edge.