Help with tRD and Memory sub timings...

[Tygler]

Hi all, this is my first post. read the recent anandtech articles detailing tRd/Performance Level and memory bandwidth with great interest. Here's the thing, on Gigabyte GA-P35-DS3P Rev. 2 I cannot post a trd of 6 at 400MHz FSB at any northbridge voltage, even with CPU underclocked and loose or auto ram timings. I feel like I'm missing a huge performance boost here, and the X38 results with trd as low as 5 have me stumped. Is this a limitation of this board in particular, the P35 northbridge in general, or am I just overlooking something. Memory subsystem is completely stable 8hrs Prime95 blend test. Showed gains in everest memory bench. Here's the best settings I've got:

Latest F9 bios
q6700 underclocked 400x6
FSB 400MHz
Multi 2.00
Primary timings: 4-4-4-11
Act to act delay (trrd) 1
Rank write to read delay 2
write to precharge delay 2
Refresh to act delay 31
Read to precharge delay 1
Static tread 7
static tread phase adjust 14

ddr2 +0.40v (2.2v I checked)
fsb +.10v
(g)mch +0.325v

Disappointing trd, though a little better with phase adjust 14. Do subtimings look freakishly low? Anyone with similar board care to way in? Anyone else, insights? Thanks!

 

[Tygler]

Oops, forgot... using 4x1GB sticks.

 

[myocardia]

Welcome to anandtech. The reason you aren't able to use the same RAM timings as Kris (the author) is because you aren't using RAM sticks that cost more than $250 each, like he used. And even if you were using exactly the same RAM, you wouldn't be able to run your timings as tight; what's possible with two sticks is never possible with four.

 

[BonzaiDuck]

I'm just seeking clarification on this, availing myself of the OP's topic.

He's using an INtel chipset. By "tRD" does he mean "tRCD?"

And is it true, with his chipset and motherboard, that tRC cannot be adjusted?

 

[myocardia]

Originally posted by: BonzaiDuck
By "tRD" does he mean "tRCD?"

No, tRD and tRCD are two separate timings.

And is it true, with his chipset and motherboard, that tRC cannot be adjusted?

I can't remember. It's been a few weeks at least, since the last time I looked in the BIOS of my GA-P35C-DS3R. I'm pretty sure, though, that tRC isn't a RAM timing/setting, unless you meant tRCD. If you meant tRCD, yes, it's adjustable.

 

[Sylvanas]

Originally posted by: myocardia

Originally posted by: BonzaiDuck
By "tRD" does he mean "tRCD?"

No, tRD and tRCD are two separate timings.

And is it true, with his chipset and motherboard, that tRC cannot be adjusted?

I can't remember. It's been a few weeks at least, since the last time I looked in the BIOS of my GA-P35C-DS3R. I'm pretty sure, though, that tRC isn't a RAM timing/setting, unless you meant tRCD. If you meant tRCD, yes, it's adjustable.

TRC should be adjustable see this article on it .

To OP, from the looks of it the subtimings you used do look quite low to begin with, I only wish I still had a sheet of paper around that I had all my Subtimings from my IP35-E. Can you provide a Memset screenshot to make things a little easier? Are you running the latest BIOS for your board? Are your Patriot sticks Micron D9's?

 

[BonzaiDuck]

My understanding of the "advanced timings" is only recently acquired.

Here are the guidelines for the integer arithmetic of DDR2 settings, as I understand them:

tRAS >= tCL + tRCD + 2

Some guides don't include the constant 2, or it isn't relevant to DDR timings (as opposed to DDR2).

tRC is known as the "bank-cycle-time," and is governed by these contraints on stability:

tRC >= tRP + tRAS

Among all the advanced timings, it is probably the only setting that can have a very large impact on bandwidth, with only a modest impact on stability. Supposedly, with DDR2 memory, tRCD gives better improvements in bandwidth than tCL, while they both affect stability about the same.

At least, this is my understanding of things, and " . . . . it works for me . . . ."

I heard elsewhere on these forums that tRC either cannot be found in the BIOS, or can't be adjusted directly in the BIOS for certain boards with the P35 chipset. I don't know whether that is general to all boards made with that chipset, some of them, or many of them.

Some other people -- notably "NefariousCaine" -- and some posters on various forums, have been able to set D9-based memory to settings that violate the relationship between tCL, tRCD and tRAS. For instance, timings like 3,3,3,5 (high voltages, low FSB around DDR2-667). I believe this derives from the "additive latency" feature of DDR2 RAM, by taking up its "slack." And _Caine tells me that he doesn't need to up the voltage on his Crucials for his motherboard to get these settings -- he's running them below 2.0V, while I need between 2.125 and 2.150V to get 3,3,3,8,1T, tRC=11. Worse than that, the monitored VDIMM is actually reported as +0.024V higher than the set values. Which means, if I set them at the warranty maximum of 2.2V, they're actually closer to 2.23V and over that limit.

Meantime, I got my Crucial Ballistix DDR2-1000 modules back as RMA replacements, and I'm not all that pleased. I have to set them a notch higher voltage-wise to get the same performance as a pair of DDR2-800 Tracers I've had in the system since burning out the 1000's in December.

 

[BonzaiDuck]

Originally posted by: Sylvanas

Originally posted by: myocardia

Originally posted by: BonzaiDuck
By "tRD" does he mean "tRCD?"

No, tRD and tRCD are two separate timings.

And is it true, with his chipset and motherboard, that tRC cannot be adjusted?

I can't remember. It's been a few weeks at least, since the last time I looked in the BIOS of my GA-P35C-DS3R. I'm pretty sure, though, that tRC isn't a RAM timing/setting, unless you meant tRCD. If you meant tRCD, yes, it's adjustable.

TRC should be adjustable see this article on it .

To OP, from the looks of it the subtimings you used do look quite low to begin with, I only wish I still had a sheet of paper around that I had all my Subtimings from my IP35-E. Can you provide a Memset screenshot to make things a little easier? Are you running the latest BIOS for your board? Are your Patriot sticks Micron D9's?

That article refers to the 680i chipset -- the one I'm using. Some member here was trying to tweak his latencies, and I'd mentioned tRC and its potential. He couldn't find it in his BIOS, and someone else suggested that it wasn't an available adjustment with that chipset and that motherboard. As I said, I can't tell if that's general to all P35 boards, or just certain boards.

 

[VirtualLarry]

I just don't bother tweaking the low-level memory timings. Too much work and risk of instability for too little actual gain.

 

[tenax]

agreed, larry..i got timings from mushkin greg specifically for my board with ranges on some of the subtimings..didn't make diddley difference and changing some were more harmful then leaving stock..only ones i worry about are the the famous "first 4"

 

[Tempered81]

if your bios won't let you change a timing you can download memset 3.4

 

[BonzaiDuck]

Basically, I agree with VirtualLarry and tenax, in principle.

A month ago I posted an excerpt from a "DDR2-memory-tweaking guide." The guide explicitly noted that it addressed timings given for the 680i chipset -- which, although i cannot be absolutely sure, provided more configuration options than other chipsets before the newer spate of Intel chipsets were released.

The timings were all evaluated according to their impact on (a) stability and (b) bandwidth improvement.

The only, single "advanced timing" of any relevance to improvement of bandwidth was tRC -- the bank-cycle-time.

Typically, DDR2 memory SPD/EPP presets make tRC default to between 5 and 10 integer values above the sum of tRP and tRAS. Therefore, tighting tCL and tRCD means that tRAS can be correspondingly tightened, and tightening tRAS means that tRC can be tightened.

The author of that "guide" was correct: setting tRC to be equal to, or an integer value above the sum of tRP and tRAS, generates very noticeable improvements in synthetic bandwidth, and what I personally observe as very noticeable improvements in performance.

But leaving tRC at its default setting masks or neutralizes any improvements that can be made in tRAS.