Haswell model specs leaked

Discussion in 'CPUs and Overclocking' started by boxleitnerb, Dec 11, 2012.

  1. IntelUser2000

    IntelUser2000 Elite Member

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    That's what I mean though. The gains you get from architectural and process related changes aren't uniform across the line, but usually focused on specific area.

    Naturally I think some sacrifice is there in absolute performance to get much better performance/watt at lower TDP and voltage segments. If high performance was slowing down back when Intel was focusing in 35W+ segments, it'll be even worse at 17W and below.

    In my opinion, that was Intel's signal that Intel was really serious about the low power market. They aren't giving it all up, but acknowledging that perhaps traditional PCs won't last forever.

    I don't buy it being due to the iGPU changes either. It shouldn't matter if you are not using it anyway and will go all to the CPU instead.

    Haswell isn't bringing lower TDP other than the process allowing performance to be better at really low power segment like the newly introduced 10W and 13W.

    The gain in battery life and such is all about the platform. I assume even ULT SKUs will have no change in clocks, but with the TDP at 15W, and the new platform power management scheme.
     
  2. cbn

    cbn Lifer

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    IDC,

    Do you happen to have a simple explanation for how these mask steppings improve clockspeed distributions and power consumption?
     
  3. IntelUser2000

    IntelUser2000 Elite Member

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    It's not a freefall reduction though. The low leakage processes usually run at higher voltages than the SP or HP meaning you use more at active but you get reduced leakage.

    Also, I'm not sure if Intel uses derivative chips on different process variations. I mean, its probable that different dies like Xeon E5 and and Sandy Bridge use different leakage transistors, but on mobile/desktop/ultra low power? Right now, they take the biggest die and cut away stuff without arranging anything around(which will be a totally new die).

    I think the reduction is purely due to segmentation and Uncore/IO changes. Oak Trail is the "focus" market which is why it looks better(think of how much better laptop SKUs look compared to Desktop ones), plus it sacrifices Uncore and IO to reach lower power. Oak Trail for example takes out 64-bit support and goes to single channel 32-bit DDR2-800 while Pine Trail supports single channel 64-bit DDR2-667. There's probably other things it downsizes like DMI links.
     
    #178 IntelUser2000, Dec 19, 2012
    Last edited: Dec 19, 2012
  4. Idontcare

    Idontcare Elite Member

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    In theory there is no difference between theory and practice, but in practice there is. :hmm:

    Mask steppings are the theoretical. The simulated. The modeled. And as with anything theoretical, there are assumptions made or implied, known and unrealized, when the masks are created.

    In short, until you have silicon in hand you really don't know for certain how the design is going to function as a product of the real-world aspects of the process node.

    New steppings don't really improve anything that wasn't already broken or an unintended speedpath bottleneck, etc.

    The design tools aren't perfect, layout isn't always optimal. Shortcuts get taken, either intentionally or unintentionally, and you don't find out until you have silicon in hand...which is why it is an inherently iterative process: design/layout/simulate -> tapeout -> validate silicon -> characterize silicon -> rationalize gap between silicon and design/layout/simulation expectations -> repeat until silicon matches target within acceptable tolerances

    And of course you can't forget this is all being done for the purposes of making money, so there is always the possibility of the cycle being cut short and management electing to rush less-than-optimized product out the door in the meantime. (B3->G0 stepping of Kentsfield, B1->B3 stepping of Barcelona)

    When a product gets rushed to market, that is when the door has been opened for a future stepping to be released that addresses things which ought to have been addressed before the product had been brought to market (in a perfect world where money and time-to-market don't matter ;))
     
  5. cbn

    cbn Lifer

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    Maybe the Haswell Ultrabook chip will have lower leakage 22nm xtors (since it is definitely unique from the other SKUs.)

    Or maybe something with dedicated lower clocks (like Pentium) and a small GPU will get the lowest leakage first?

    Tough to figure out what could happen since I don't have a point of reference. Intel Ark just lists "lithography" as the spec, not the process tech :(

    Anandtech does list different die sizes for dual core, quad core, GT1, GT2, etc.

    http://www.anandtech.com/show/5876/the-rest-of-the-ivy-bridge-die-sizes

    But I can't find the info on the die cutting.
     
  6. IntelUser2000

    IntelUser2000 Elite Member

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    Perhaps it will be different for dual core GT3 ULT but I'm still not sure.

    It's easy to figure out what "derivatives" are compared to full new dies.

    It's simple at looking at how the cores are arranged. First, look at this awesome RWT article: http://www.realworldtech.com/sandy-bridge-circuits/

    Go to Google.com and search for the die shots of Sandy Bridge and Sandy Bridge EP. If you compare them side by side and look at it closely, you'll see that it can't be a simple cut. The EP's cores and caches are in different location to each other. Sandy Bridge has the cores laid out side by side, with the L3 cache on the bottom of the cores. Sandy Bridge EP has the cores surrounding the L3 cache at the center.

    Not rearranging the locations make it lot easier to get it working. Validation times are lower, and there are less effort to do it. Changing the layout likely requires figuring out timing on the wires and circuits for example. Now the derivatives DO take a bit of time to make, but way shorter than complete new dies. These chips have hundreds of millions of transistors and wires you know. :)

    But you are talking about doing lot more than that, by using transistor with a different characteristic.
     
    #181 IntelUser2000, Dec 20, 2012
    Last edited: Dec 20, 2012
  7. cbn

    cbn Lifer

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    For some reason I was thinking the Haswell die (for ultrabooks) integrated the PCH. In fact, it is a MCP (two dies on a package).

    So it is not unique as I was thinking.

    http://www.anandtech.com/show/5078/...abooks-gt3-gpu-for-mobile-lga1150-for-desktop

     
    #182 cbn, Dec 21, 2012
    Last edited: Dec 21, 2012
  8. cbn

    cbn Lifer

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    That is a great article. Thank you for the link.


    During my search today I also noticed you started a thread discussing cut lines and the derivative process ---> http://forums.anandtech.com/showthread.php?t=2234017

    Good info!

    But how does Intel connect the cut die pieces back together?
     
    #183 cbn, Dec 21, 2012
    Last edited: Dec 21, 2012
  9. IntelUser2000

    IntelUser2000 Elite Member

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    Of course you can't attach them back physically, its done before. Seperate die means that each version has its own wafer. The "cut and paste" process is likely done on a computer and that will turn into its unique mask.

    Compare to printing. You can't attach the cut paper pieces back together. You do it on the computer before printing to make the shapes you want.
     
  10. jpiniero

    jpiniero Diamond Member

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    Yeah. It's going to happen sooner rather than later though. Perhaps Broadwell?
     
  11. IntelUser2000

    IntelUser2000 Elite Member

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    Skylake at the earliest according to PCWatch, and I agree with them too. It's with Tock such changes happen.
     
  12. Fjodor2001

    Fjodor2001 Diamond Member

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    So what discrete components will be left on the motherboard after that?

    Will we reach a solution which more or less consists of only one chip and connectors?

    And a lot of connectors can also be removed on some motherboard models, e.g. if only iGPU and soldered on board RAM is used (i.e. no PCIE or RAM slots).

    See e.g. Intel DH77DF board component diagram:

    http://www.intel.com/support/motherboards/desktop/dh77df/sb/CS-033202.htm
     
  13. IntelUser2000

    IntelUser2000 Elite Member

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    Little late, but I hope you still get to read it.

    You can see its under the acronym "FMB". FMB stands for "Flexible Mainboard" or something in that form. FMB is basically a power guideline for sockets and motherboards.

    A/B/C/D each corresponds to different power guidelines. You can see the alphabets only vary when TDP numbers are different. Unless you are involved in designing those motherboards, its not that meaningful to you.
     
  14. jpiniero

    jpiniero Diamond Member

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    That does sound more realistic.

    I think so. And by 'one chip', I mean everything, including ram and disk. That will take awhile to get to that point though.
     
  15. cbn

    cbn Lifer

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    I know HP has released on good amount of information on stacking the storage with the CPU.

    How about Intel? Anyone have any good links on this? (It would be very interesting to understand how these memory developments could affect their processor design)
     
  16. cbn

    cbn Lifer

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    Thanks for explanation.

    So basically a lot of the local interconnects could be re-used, but other larger area interconnects would have to be re-designed.
     
  17. cbn

    cbn Lifer

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    So Skylake will probably have the PCH (<--and this portion will selectively be low leakage process?) and digital wifi integrated?

    So this leaves the question of how the master die will be arranged on how the cutlines will be drawn.
     
  18. IntelUser2000

    IntelUser2000 Elite Member

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    WiFi integration is further out, due to the fact that engineers still need to solve issues with interference. The prototype Atom clocked similar to WiFi frequency which supposedly helps reduce interference. It probably is even longer out for Core chips, and will come to Atom first. Tablets and Ultrabooks don't need so much space saving as to integrate the WiFi chip, unlike Smartphones.

    Topic: Intel expects Haswell to only ramp to 20% of the desktop market in second half of next year. That's pretty slow compared to Sandy Bridge and Ivy Bridge. The reason is likely due to high inventory levels of Ivy Bridge chips combined with less than stellar specifications of Haswell desktop chips.

    Even if Intel doesn't abandon socketed LGA chips in the future, they will need really good ideas to ensure the enthusiast/socketable market will grow. Or it will be inevitable that they will be forced to kill it.
     
  19. cbn

    cbn Lifer

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    That is a low percent for desktop and I have to wonder if Intel is planning to put the mainstream core processor on the low power/low leakage process at some point because of that?

    Such a move would increase the separation between the mainstream core processors and the E-series on the big LGA socket.

    If that happened, the E-series processors would effectively have to take over the void left by the mainstream unlocked multiplier K chips. This could be handled by Intel having more chips like the i7-3820 (a true quad core with its own die) and a drop in price of the mainboards for the large socket.

    That leaves the mainstream core processors to speculate about. One thing I would be concerned about is a reduction in turbo performance for these new low leakage ultra book/tablet chips. As I understand things, low leakage = lower max clocks, but better overall energy efficiency. But maybe a move to a fanless design (and the form factor enabled by that) would more than offset the loss in max performance for the old top bin?
     
  20. mikk

    mikk Golden Member

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    20% is no surprise really because Intel will launch only Quadcores in May, ULT models in Q3 and dualcores in Q4.
     
  21. IntelUser2000

    IntelUser2000 Elite Member

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    20% is for Desktop.
     
  22. mrmt

    mrmt Diamond Member

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    Would you have a source for this number? It's H213, not H113? Because it doesn't make sense to churn out old designs at that rate when you have a new one on the wings. Plus they are not sitting on huge inventories right now, they can simply scale back manufacturing to make room for HSW. In fact, they are scaling back manufacturing.
     
  23. IntelUser2000

    IntelUser2000 Elite Member

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    Fudzilla, but I've seen their estimates for Ivy Bridge, and they weren't wrong, so I don't assume they are now either. And yes, its for 2H 2013. For 1H 2013 its mere 5%.

    They've said that 70% of inventory is due to Ivy Bridge, so even if its not high, they still need to clear that out.

    mikk might be right in a general sense then. Ivy Bridge got dual core desktop chips quite fast, but we may not see that with Haswell. Dual cores are probably still very important in terms of volume desktop shipments for Intel.

    BTW, GT3 is coming at similar time to GT2 variants for the mobile quad core. We just don't have it leaked, that's all.
     
    #198 IntelUser2000, Dec 25, 2012
    Last edited: Dec 25, 2012
  24. cbn

    cbn Lifer

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    One thing Intel could do is sell unlocked multiplier dual core chips.

    Add $15 premium to Pentium or i3 and I would definitely consider buying.
     
  25. inf64

    inf64 Platinum Member

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    #200 inf64, Dec 26, 2012
    Last edited: Dec 26, 2012